Function: double std::uniform_real_distribution<double>::operator()<std::mersenne_twister_engine<uns ... | Module: exec | Source: random.h:1726-1823 [...] | Coverage: 0.01% |
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Function: double std::uniform_real_distribution<double>::operator()<std::mersenne_twister_engine<uns ... | Module: exec | Source: random.h:1726-1823 [...] | Coverage: 0.01% |
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/usr/lib/gcc/x86_64-redhat-linux/8/../../../../include/c++/8/bits/random.h: 1726 - 1823 |
-------------------------------------------------------------------------------- |
1726: { return _M_a; } |
1727: |
1728: result_type |
1729: b() const |
1730: { return _M_b; } |
[...] |
1814: { return this->operator()(__urng, _M_param); } |
[...] |
1823: return (__aurng() * (__p.b() - __p.a())) + __p.a(); |
/usr/lib/gcc/x86_64-redhat-linux/8/../../../../include/c++/8/bits/random.tcc: 401 - 3338 |
-------------------------------------------------------------------------------- |
401: for (size_t __k = 0; __k < (__n - __m); ++__k) |
402: { |
403: _UIntType __y = ((_M_x[__k] & __upper_mask) |
404: | (_M_x[__k + 1] & __lower_mask)); |
405: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
406: ^ ((__y & 0x01) ? __a : 0)); |
407: } |
408: |
409: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
410: { |
411: _UIntType __y = ((_M_x[__k] & __upper_mask) |
412: | (_M_x[__k + 1] & __lower_mask)); |
413: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
414: ^ ((__y & 0x01) ? __a : 0)); |
415: } |
416: |
417: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
418: | (_M_x[0] & __lower_mask)); |
419: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
420: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
455: if (_M_p >= state_size) |
456: _M_gen_rand(); |
457: |
458: // Calculate o(x(i)). |
459: result_type __z = _M_x[_M_p++]; |
460: __z ^= (__z >> __u) & __d; |
461: __z ^= (__z << __s) & __b; |
462: __z ^= (__z << __t) & __c; |
463: __z ^= (__z >> __l); |
[...] |
3323: const size_t __log2r = std::log(__r) / std::log(2.0L); |
3324: const size_t __m = std::max<size_t>(1UL, |
3325: (__b + __log2r - 1UL) / __log2r); |
3326: _RealType __ret; |
3327: _RealType __sum = _RealType(0); |
3328: _RealType __tmp = _RealType(1); |
3329: for (size_t __k = __m; __k != 0; --__k) |
3330: { |
3331: __sum += _RealType(__urng() - __urng.min()) * __tmp; |
3332: __tmp *= __r; |
3333: } |
3334: __ret = __sum / __tmp; |
3335: if (__builtin_expect(__ret >= _RealType(1), 0)) |
3336: { |
3337: #if _GLIBCXX_USE_C99_MATH_TR1 |
3338: __ret = std::nextafter(_RealType(1), _RealType(0)); |
/usr/lib/gcc/x86_64-redhat-linux/8/../../../../include/c++/8/cmath: 343 - 343 |
-------------------------------------------------------------------------------- |
343: { return __builtin_logl(__x); } |
0x40b5c0 PUSH %RBP |
0x40b5c1 MOV %RSP,%RBP |
0x40b5c4 PUSH %R14 |
0x40b5c6 PUSH %RBX |
0x40b5c7 SUB $0x40,%RSP |
0x40b5cb MOV %RSI,%R14 |
0x40b5ce MOV %RDI,%RBX |
0x40b5d1 FLDS 0xd8809(%RIP) |
0x40b5d7 FSTPT (%RSP) |
0x40b5da CALL 4ce790 <logl> |
0x40b5df FSTPT -0x34(%RBP) |
0x40b5e2 FLDS 0xd87fc(%RIP) |
0x40b5e8 FSTPT (%RSP) |
0x40b5eb CALL 4ce790 <logl> |
0x40b5f0 FLDT -0x34(%RBP) |
0x40b5f3 FDIVP %ST0,%ST1 |
0x40b5f5 FLDS 0xd87ed(%RIP) |
0x40b5fb XOR %ECX,%ECX |
0x40b5fd FXCH %ST1 |
0x40b5ff FUCOMI %ST1,%ST0 |
0x40b601 FLDZ |
0x40b603 FCMOVNB %ST2,%ST0 |
0x40b605 FSTP %ST2 |
0x40b607 FSUBP %ST0,%ST1 |
0x40b609 FISTTP -0x28(%RBP) |
0x40b60c SETAE %CL |
0x40b60f SAL $0x3f,%RCX |
0x40b613 XOR -0x28(%RBP),%RCX |
0x40b617 LEA 0x34(%RCX),%RAX |
0x40b61b MOV %RAX,%RDX |
0x40b61e OR %RCX,%RDX |
0x40b621 SHR $0x20,%RDX |
0x40b625 JE 40b62e |
0x40b627 XOR %EDX,%EDX |
0x40b629 DIV %RCX |
0x40b62c JMP 40b632 |
0x40b62e XOR %EDX,%EDX |
0x40b630 DIV %ECX |
0x40b632 CMP $0x1,%RAX |
0x40b636 ADC $-0x1,%RAX |
0x40b63a MOV 0x1380(%R14),%RSI |
0x40b641 LEA 0x700(%R14),%RCX |
0x40b648 VMOVSD 0xd7fb0(%RIP),%XMM1 |
0x40b650 VXORPD %XMM0,%XMM0,%XMM0 |
0x40b654 XOR %EDX,%EDX |
0x40b656 VPBROADCASTQ 0xd7fb1(%RIP),%YMM2 |
0x40b65f VPBROADCASTQ 0xd7fb0(%RIP),%YMM3 |
0x40b668 VPBROADCASTQ 0xd7faf(%RIP),%YMM4 |
0x40b671 VPBROADCASTQ 0xd7fae(%RIP),%YMM5 |
0x40b67a MOV $0x7,%DIL |
0x40b67d KMOVB %EDI,%K1 |
0x40b681 JMP 40b6ff |
0x40b683 NOPW %CS:(%RAX,%RAX,1) |
(60) 0x40b690 MOV (%R14,%RSI,8),%RDI |
(60) 0x40b694 MOV %RDI,%R8 |
(60) 0x40b697 SHR $0xb,%R8 |
(60) 0x40b69b MOV %R8D,%R8D |
(60) 0x40b69e XOR %RDI,%R8 |
(60) 0x40b6a1 MOV %R8D,%EDI |
(60) 0x40b6a4 SAL $0x7,%EDI |
(60) 0x40b6a7 AND $-0x62d3a980,%EDI |
(60) 0x40b6ad XOR %R8,%RDI |
(60) 0x40b6b0 MOV %EDI,%R8D |
(60) 0x40b6b3 SAL $0xf,%R8D |
(60) 0x40b6b7 AND $-0x103a0000,%R8D |
(60) 0x40b6be XOR %RDI,%R8 |
(60) 0x40b6c1 MOV %R8,%RDI |
(60) 0x40b6c4 SHR $0x12,%RDI |
(60) 0x40b6c8 XOR %R8,%RDI |
(60) 0x40b6cb VCVTUSI2SD %RDI,%XMM12,%XMM9 |
(60) 0x40b6d1 INC %RSI |
(60) 0x40b6d4 VMOVSD %XMM1,-0x20(%RBP) |
(60) 0x40b6d9 FLDL -0x20(%RBP) |
(60) 0x40b6dc FMULS 0xd86fe(%RIP) |
(60) 0x40b6e2 VFMADD231SD %XMM9,%XMM1,%XMM0 |
(60) 0x40b6e7 FSTPL -0x18(%RBP) |
(60) 0x40b6ea VMOVSD -0x18(%RBP),%XMM1 |
(60) 0x40b6ef LEA 0x1(%RDX),%RDI |
(60) 0x40b6f3 CMP %RAX,%RDX |
(60) 0x40b6f6 MOV %RDI,%RDX |
(60) 0x40b6f9 JE 40b8b0 |
(60) 0x40b6ff CMP $0x270,%RSI |
(60) 0x40b706 JB 40b690 |
(60) 0x40b708 MOV $-0x4,%RSI |
(60) 0x40b70f NOP |
(61) 0x40b710 VMOVDQU 0x28(%R14,%RSI,8),%YMM9 |
(61) 0x40b717 VPSRLQ $0x1,%YMM9,%YMM10 |
(61) 0x40b71d VPAND %YMM3,%YMM10,%YMM10 |
(61) 0x40b721 VPSRLQ $0x1,0x20(%R14,%RSI,8),%YMM11 |
(61) 0x40b72a VPAND %YMM4,%YMM11,%YMM11 |
(61) 0x40b72e VPTERNLOGQ $0x56,0xc88(%R14,%RSI,8),%YMM10,%YMM11 |
(61) 0x40b73a VMOVDQU 0x48(%R14,%RSI,8),%YMM10 |
(61) 0x40b741 VPTESTMQ %YMM2,%YMM9,%K2 |
(61) 0x40b747 VPXORQ %YMM5,%YMM11,%YMM11{%K2} |
(61) 0x40b74d VMOVDQU %YMM11,0x20(%R14,%RSI,8) |
(61) 0x40b754 VPSRLQ $0x1,%YMM10,%YMM9 |
(61) 0x40b75a VPAND %YMM3,%YMM9,%YMM9 |
(61) 0x40b75e VPSRLQ $0x1,0x40(%R14,%RSI,8),%YMM11 |
(61) 0x40b767 VPAND %YMM4,%YMM11,%YMM11 |
(61) 0x40b76b VPTERNLOGQ $0x56,0xca8(%R14,%RSI,8),%YMM9,%YMM11 |
(61) 0x40b777 VPTESTMQ %YMM2,%YMM10,%K2 |
(61) 0x40b77d VPXORQ %YMM5,%YMM11,%YMM11{%K2} |
(61) 0x40b783 VMOVDQU %YMM11,0x40(%R14,%RSI,8) |
(61) 0x40b78a ADD $0x8,%RSI |
(61) 0x40b78e CMP $0xdc,%RSI |
(61) 0x40b795 JB 40b710 |
(60) 0x40b79b VPBLENDD $0x3f,0x700(%R14),%YMM8,%YMM8 |
(60) 0x40b7a5 VPBLENDD $0x3f,0x708(%R14),%YMM6,%YMM6 |
(60) 0x40b7af VPSRLQ $0x1,%YMM6,%YMM9 |
(60) 0x40b7b4 VPAND %YMM3,%YMM9,%YMM9 |
(60) 0x40b7b8 VPSRLQ $0x1,%YMM8,%YMM10 |
(60) 0x40b7be VPBLENDD $0x3f,0x1368(%R14),%YMM7,%YMM7 |
(60) 0x40b7c8 VPTERNLOGQ $-0x14,%YMM4,%YMM9,%YMM10 |
(60) 0x40b7cf VPTESTMQ %YMM2,%YMM6,%K2 |
(60) 0x40b7d5 VMOVDQA64 %YMM5,%YMM9{%K2}{z} |
(60) 0x40b7db VPTERNLOGQ $-0x6a,%YMM10,%YMM7,%YMM9 |
(60) 0x40b7e2 VMOVDQU64 %YMM9,(%RCX){%K1} |
(60) 0x40b7e8 MOV 0x718(%R14),%RDI |
(60) 0x40b7ef XOR %ESI,%ESI |
(60) 0x40b7f1 NOPW %CS:(%RAX,%RAX,1) |
(62) 0x40b800 VMOVDQU 0x720(%R14,%RSI,1),%YMM9 |
(62) 0x40b80a VPSRLQ $0x1,%YMM9,%YMM10 |
(62) 0x40b810 VPAND %YMM3,%YMM10,%YMM10 |
(62) 0x40b814 VPBROADCASTQ %RDI,%YMM11 |
(62) 0x40b81a VPBLENDD $-0x40,%YMM11,%YMM9,%YMM11 |
(62) 0x40b820 VPSRLQ $0x1,%YMM11,%YMM11 |
(62) 0x40b826 VPERMQ $-0x6d,%YMM11,%YMM11 |
(62) 0x40b82c VPAND %YMM4,%YMM11,%YMM11 |
(62) 0x40b830 VPTERNLOGQ $0x56,(%R14,%RSI,1),%YMM10,%YMM11 |
(62) 0x40b838 VPTESTMQ %YMM2,%YMM9,%K2 |
(62) 0x40b83e VPXORQ %YMM5,%YMM11,%YMM11{%K2} |
(62) 0x40b844 VMOVDQU %YMM11,0x718(%R14,%RSI,1) |
(62) 0x40b84e MOV 0x738(%R14,%RSI,1),%RDI |
(62) 0x40b856 ADD $0x20,%RSI |
(62) 0x40b85a CMP $0xc60,%RSI |
(62) 0x40b861 JNE 40b800 |
(60) 0x40b863 MOV 0x1378(%R14),%RSI |
(60) 0x40b86a MOV (%R14),%RDI |
(60) 0x40b86d MOV %EDI,%R8D |
(60) 0x40b870 SHR $0x1,%R8D |
(60) 0x40b873 AND $0x3fffffff,%R8D |
(60) 0x40b87a SHR $0x1,%RSI |
(60) 0x40b87d AND $-0x40000000,%RSI |
(60) 0x40b884 OR %R8,%RSI |
(60) 0x40b887 XOR 0xc60(%R14),%RSI |
(60) 0x40b88e MOV %EDI,%R8D |
(60) 0x40b891 AND $0x1,%R8D |
(60) 0x40b895 NEG %R8D |
(60) 0x40b898 AND $-0x66f74f21,%R8D |
(60) 0x40b89f XOR %RSI,%R8 |
(60) 0x40b8a2 MOV %R8,0x1378(%R14) |
(60) 0x40b8a9 XOR %ESI,%ESI |
(60) 0x40b8ab JMP 40b694 |
0x40b8b0 MOV %RSI,0x1380(%R14) |
0x40b8b7 VDIVSD %XMM1,%XMM0,%XMM0 |
0x40b8bb VUCOMISD 0xd7d3d(%RIP),%XMM0 |
0x40b8c3 JAE 40b8e7 |
0x40b8c5 VMOVSD (%RBX),%XMM2 |
0x40b8c9 VMOVSD 0x8(%RBX),%XMM1 |
0x40b8ce VSUBSD %XMM2,%XMM1,%XMM1 |
0x40b8d2 VFMADD213SD %XMM2,%XMM0,%XMM1 |
0x40b8d7 VMOVAPD %XMM1,%XMM0 |
0x40b8db ADD $0x40,%RSP |
0x40b8df POP %RBX |
0x40b8e0 POP %R14 |
0x40b8e2 POP %RBP |
0x40b8e3 VZEROUPPER |
0x40b8e6 RET |
0x40b8e7 VMOVSD 0xd7d11(%RIP),%XMM0 |
0x40b8ef VXORPD %XMM1,%XMM1,%XMM1 |
0x40b8f3 VZEROUPPER |
0x40b8f6 CALL 4ce7b0 <nextafter> |
0x40b8fb JMP 40b8c5 |
0x40b8fd NOPL (%RAX) |
Path / |
Source file and lines | random.h:1726-1823 |
Module | exec |
nb instructions | 74 |
nb uops | 116 |
loop length | 288 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 4 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 19.33 cycles |
front end | 19.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.50 | 9.50 | 9.00 | 9.00 | 7.00 | 9.50 | 9.50 | 3.50 | 3.50 | 7.00 | 4.00 | 9.00 |
cycles | 9.50 | 9.50 | 9.00 | 9.00 | 7.00 | 9.50 | 9.50 | 3.50 | 3.50 | 7.00 | 4.00 | 9.00 |
Cycles executing div or sqrt instructions | 24.50 |
FE+BE cycles | 26.24-25.29 |
Stall cycles | 10.07-9.12 |
ROB full (events) | 12.28-11.33 |
Front-end | 19.33 |
Dispatch | 9.50 |
DIV/SQRT | 24.50 |
Overall L1 | 24.50 |
all | 11% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 27% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 75% |
all | 17% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 29% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 15% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 21% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | 12% |
div/sqrt | 10% |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
FLDS 0xd8809(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
FSTPT (%RSP) | 7 | 0.75 | 0.75 | 0.67 | 0.67 | 1 | 0.75 | 0.75 | 0 | 0 | 1 | 0 | 0.67 | 4 | 5 |
CALL 4ce790 <logl> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
FSTPT -0x34(%RBP) | 7 | 0.75 | 0.75 | 0.67 | 0.67 | 1 | 0.75 | 0.75 | 0 | 0 | 1 | 0 | 0.67 | 4 | 5 |
FLDS 0xd87fc(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
FSTPT (%RSP) | 7 | 0.75 | 0.75 | 0.67 | 0.67 | 1 | 0.75 | 0.75 | 0 | 0 | 1 | 0 | 0.67 | 4 | 5 |
CALL 4ce790 <logl> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
FLDT -0x34(%RBP) | 4 | 0.50 | 1 | 0.67 | 0.67 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.67 | 4 | 2 |
FDIVP %ST0,%ST1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14-16 | 4.50 |
FLDS 0xd87ed(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
FXCH %ST1 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
FUCOMI %ST1,%ST0 | 3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
FLDZ | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
FCMOVNB %ST2,%ST0 | 4 | 1 | 0.50 | 0 | 0 | 0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 3 | 1.50 |
FSTP %ST2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
FSUBP %ST0,%ST1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
FISTTP -0x28(%RBP) | 3 | 0 | 0 | 0.33 | 0.33 | 0.50 | 1 | 0 | 0 | 0 | 0.50 | 0 | 0.33 | 7 | 1 |
SETAE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SAL $0x3f,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR -0x28(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 |
LEA 0x34(%RCX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 40b62e <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x6e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 40b632 <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x72> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP $0x1,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADC $-0x1,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x1380(%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x700(%R14),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xd7fb0(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ 0xd7fb1(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ 0xd7fb0(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ 0xd7faf(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ 0xd7fae(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV $0x7,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KMOVB %EDI,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JMP 40b6ff <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x13f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0x1380(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VDIVSD %XMM1,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VUCOMISD 0xd7d3d(%RIP),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JAE 40b8e7 <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x327> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RBX),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
ADD $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
VMOVSD 0xd7d11(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4ce7b0 <nextafter> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
JMP 40b8c5 <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x305> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | random.h:1726-1823 |
Module | exec |
nb instructions | 74 |
nb uops | 116 |
loop length | 288 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 4 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 19.33 cycles |
front end | 19.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.50 | 9.50 | 9.00 | 9.00 | 7.00 | 9.50 | 9.50 | 3.50 | 3.50 | 7.00 | 4.00 | 9.00 |
cycles | 9.50 | 9.50 | 9.00 | 9.00 | 7.00 | 9.50 | 9.50 | 3.50 | 3.50 | 7.00 | 4.00 | 9.00 |
Cycles executing div or sqrt instructions | 24.50 |
FE+BE cycles | 26.24-25.29 |
Stall cycles | 10.07-9.12 |
ROB full (events) | 12.28-11.33 |
Front-end | 19.33 |
Dispatch | 9.50 |
DIV/SQRT | 24.50 |
Overall L1 | 24.50 |
all | 11% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 27% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 75% |
all | 17% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 29% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 15% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 21% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | 12% |
div/sqrt | 10% |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
FLDS 0xd8809(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
FSTPT (%RSP) | 7 | 0.75 | 0.75 | 0.67 | 0.67 | 1 | 0.75 | 0.75 | 0 | 0 | 1 | 0 | 0.67 | 4 | 5 |
CALL 4ce790 <logl> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
FSTPT -0x34(%RBP) | 7 | 0.75 | 0.75 | 0.67 | 0.67 | 1 | 0.75 | 0.75 | 0 | 0 | 1 | 0 | 0.67 | 4 | 5 |
FLDS 0xd87fc(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
FSTPT (%RSP) | 7 | 0.75 | 0.75 | 0.67 | 0.67 | 1 | 0.75 | 0.75 | 0 | 0 | 1 | 0 | 0.67 | 4 | 5 |
CALL 4ce790 <logl> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
FLDT -0x34(%RBP) | 4 | 0.50 | 1 | 0.67 | 0.67 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.67 | 4 | 2 |
FDIVP %ST0,%ST1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14-16 | 4.50 |
FLDS 0xd87ed(%RIP) | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
FXCH %ST1 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
FUCOMI %ST1,%ST0 | 3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
FLDZ | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
FCMOVNB %ST2,%ST0 | 4 | 1 | 0.50 | 0 | 0 | 0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 3 | 1.50 |
FSTP %ST2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
FSUBP %ST0,%ST1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
FISTTP -0x28(%RBP) | 3 | 0 | 0 | 0.33 | 0.33 | 0.50 | 1 | 0 | 0 | 0 | 0.50 | 0 | 0.33 | 7 | 1 |
SETAE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SAL $0x3f,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR -0x28(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 |
LEA 0x34(%RCX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
OR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x20,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
JE 40b62e <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x6e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %RCX | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
JMP 40b632 <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x72> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %ECX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP $0x1,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADC $-0x1,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x1380(%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x700(%R14),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xd7fb0(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ 0xd7fb1(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ 0xd7fb0(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ 0xd7faf(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ 0xd7fae(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV $0x7,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KMOVB %EDI,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JMP 40b6ff <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x13f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0x1380(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VDIVSD %XMM1,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VUCOMISD 0xd7d3d(%RIP),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JAE 40b8e7 <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x327> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RBX),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
ADD $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
VMOVSD 0xd7d11(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4ce7b0 <nextafter> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
JMP 40b8c5 <_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_+0x305> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼double std::uniform_real_distribution | 0.01 | 0 |
▼Loop 60 - random.tcc:401-3332 - exec– | 0 | 0.01 |
○Loop 61 - random.tcc:401-406 - exec | 0 | 0 |
○Loop 62 - random.tcc:409-414 - exec | 0 | 0 |