Loop Id: 845 | Module: exec | Source: stl_algobase.h:918-918 [...] | Coverage: 0.04% |
---|
Loop Id: 845 | Module: exec | Source: stl_algobase.h:918-918 [...] | Coverage: 0.04% |
---|
0x46e046 MOVQ $0,0x10(%RAX) [1] |
0x46e04e ADD $0xc0,%RAX |
0x46e054 VMOVUPD %XMM12,-0xc0(%RAX) [2] |
0x46e05c VMOVUPD %XMM12,-0xa8(%RAX) [2] |
0x46e064 MOVQ $0,-0x98(%RAX) [2] |
0x46e06f VMOVUPD %XMM12,-0x90(%RAX) [2] |
0x46e077 MOVQ $0,-0x80(%RAX) [2] |
0x46e07f VMOVUPD %XMM12,-0x78(%RAX) [2] |
0x46e084 MOVQ $0,-0x68(%RAX) [2] |
0x46e08c VMOVUPD %XMM12,-0x60(%RAX) [2] |
0x46e091 MOVQ $0,-0x50(%RAX) [2] |
0x46e099 VMOVUPD %XMM12,-0x48(%RAX) [2] |
0x46e09e MOVQ $0,-0x38(%RAX) [2] |
0x46e0a6 VMOVUPD %XMM12,-0x30(%RAX) [2] |
0x46e0ab MOVQ $0,-0x20(%RAX) [2] |
0x46e0b3 VMOVUPD %XMM12,-0x18(%RAX) [2] |
0x46e0b8 MOVQ $0,-0x8(%RAX) [2] |
0x46e0c0 CMP %RAX,%R9 |
0x46e0c3 JNE 46e046 |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183 |
-------------------------------------------------------------------------------- |
183: return (const_cast<T1&>(a) = b); |
/usr/include/c++/13.1.1/bits/stl_algobase.h: 918 - 918 |
-------------------------------------------------------------------------------- |
918: for (; __first != __last; ++__first) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►57.14+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:48 | exec |
○ | qmcplusplus::build_WaveFunctio[...] | WaveFunction.cpp:83 | exec |
○ | main._omp_fn.0 | miniqmc.cpp:389 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►42.86+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:48 | exec |
○ | qmcplusplus::build_WaveFunctio[...] | WaveFunction.cpp:84 | exec |
○ | main._omp_fn.0 | miniqmc.cpp:389 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.40 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 3.00 |
Bottlenecks | P4, |
Function | miniqmcreference::DiracDeterminantRef |
Source | OperatorTags.h:183-183,stl_algobase.h:918-918 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 2.50 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 16.00 |
P4 cycles | 0.50 |
P5 cycles | 0.50 |
P6 cycles | 5.33 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 16.07 |
Stall cycles (UFS) | 11.41 |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 0.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 192.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 50.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 50.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 15.63 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 15.63 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.40 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 3.00 |
Bottlenecks | P4, |
Function | miniqmcreference::DiracDeterminantRef |
Source | OperatorTags.h:183-183,stl_algobase.h:918-918 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 2.50 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 16.00 |
P4 cycles | 0.50 |
P5 cycles | 0.50 |
P6 cycles | 5.33 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 16.07 |
Stall cycles (UFS) | 11.41 |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 0.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 192.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 50.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 50.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 15.63 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 15.63 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | miniqmcreference::DiracDeterminantRef |
Source file and lines | stl_algobase.h:918-918 |
Module | exec |
nb instructions | 19 |
nb uops | 18 |
loop length | 127 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 5.33 | 5.33 | 16.00 | 0.50 | 0.50 | 5.33 |
cycles | 0.50 | 0.50 | 5.33 | 5.33 | 16.00 | 0.50 | 0.50 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 16.07 |
Stall cycles | 11.41 |
SB full (events) | 15.88 |
Front-end | 4.50 |
Dispatch | 16.00 |
Data deps. | 1.00 |
Overall L1 | 16.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 15% |
load | NA (no load vectorizable/vectorized instructions) |
store | 15% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOVQ $0,0x10(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
ADD $0xc0,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVUPD %XMM12,-0xc0(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM12,-0xa8(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x98(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x90(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x80(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x78(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x68(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x60(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x50(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x48(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x38(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x30(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x20(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x18(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x8(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
CMP %RAX,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 46e046 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | miniqmcreference::DiracDeterminantRef |
Source file and lines | stl_algobase.h:918-918 |
Module | exec |
nb instructions | 19 |
nb uops | 18 |
loop length | 127 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 5.33 | 5.33 | 16.00 | 0.50 | 0.50 | 5.33 |
cycles | 0.50 | 0.50 | 5.33 | 5.33 | 16.00 | 0.50 | 0.50 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 16.07 |
Stall cycles | 11.41 |
SB full (events) | 15.88 |
Front-end | 4.50 |
Dispatch | 16.00 |
Data deps. | 1.00 |
Overall L1 | 16.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 15% |
load | NA (no load vectorizable/vectorized instructions) |
store | 15% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOVQ $0,0x10(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
ADD $0xc0,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVUPD %XMM12,-0xc0(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM12,-0xa8(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x98(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x90(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x80(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x78(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x68(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x60(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x50(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x48(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x38(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x30(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x20(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
VMOVUPD %XMM12,-0x18(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVQ $0,-0x8(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
CMP %RAX,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 46e046 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |