Loop Id: 658 | Module: exec | Source: MultiBsplineRef.hpp:66-74 | Coverage: 0.01% |
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Loop Id: 658 | Module: exec | Source: MultiBsplineRef.hpp:66-74 | Coverage: 0.01% |
---|
0x450bae VMULSD (%RDI),%XMM15,%XMM6 |
0x450bb2 TEST %R14,%R14 |
0x450bb5 JE 450eb0 |
0x450bbb CMPQ $0x6,0xc0(%RSP) |
0x450bc4 JBE 450fc0 |
0x450bca LEA -0x40(%R13),%RSI |
0x450bce LEA (%RAX,%R12,1),%R9 |
0x450bd2 VBROADCASTSD %XMM6,%ZMM16 |
0x450bd8 XOR %R8D,%R8D |
0x450bdb SHR $0x6,%RSI |
0x450bdf LEA (%R9,%R12,1),%R15 |
0x450be3 INC %RSI |
0x450be6 LEA (%R15,%R12,1),%R10 |
0x450bea AND $0x3,%ESI |
0x450bed JE 450ca0 |
0x450bf3 CMP $0x1,%RSI |
0x450bf7 JE 450c63 |
0x450bf9 CMP $0x2,%RSI |
0x450bfd JE 450c2f |
0x450bff VMULPD (%R9),%ZMM4,%ZMM0 |
0x450c05 MOV $0x40,%R8D |
0x450c0b VMULPD (%R10),%ZMM2,%ZMM17 |
0x450c11 VFMADD231PD (%RAX),%ZMM5,%ZMM0 |
0x450c17 VFMADD231PD (%R15),%ZMM3,%ZMM17 |
0x450c1d VADDPD %ZMM17,%ZMM0,%ZMM1 |
0x450c23 VFMADD213PD (%RCX),%ZMM16,%ZMM1 |
0x450c29 VMOVUPD %ZMM1,(%RCX) |
0x450c2f VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 |
0x450c36 VMULPD (%R10,%R8,1),%ZMM2,%ZMM18 |
0x450c3d VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 |
0x450c44 VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM18 |
0x450c4b VADDPD %ZMM18,%ZMM0,%ZMM1 |
0x450c51 VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 |
0x450c58 VMOVUPD %ZMM1,(%RCX,%R8,1) |
0x450c5f ADD $0x40,%R8 |
0x450c63 VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 |
0x450c6a VMULPD (%R10,%R8,1),%ZMM2,%ZMM19 |
0x450c71 VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 |
0x450c78 VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM19 |
0x450c7f VADDPD %ZMM19,%ZMM0,%ZMM1 |
0x450c85 VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 |
0x450c8c VMOVUPD %ZMM1,(%RCX,%R8,1) |
0x450c93 ADD $0x40,%R8 |
0x450c97 CMP %R13,%R8 |
0x450c9a JE 450d82 |
(661) 0x450ca0 VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 |
(661) 0x450ca7 VMULPD (%R10,%R8,1),%ZMM2,%ZMM20 |
(661) 0x450cae VMULPD 0x40(%R10,%R8,1),%ZMM2,%ZMM21 |
(661) 0x450cb6 VMULPD 0x80(%R10,%R8,1),%ZMM2,%ZMM22 |
(661) 0x450cbe VMULPD 0xc0(%R10,%R8,1),%ZMM2,%ZMM23 |
(661) 0x450cc6 VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 |
(661) 0x450ccd VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM20 |
(661) 0x450cd4 VFMADD231PD 0x40(%R15,%R8,1),%ZMM3,%ZMM21 |
(661) 0x450cdc VFMADD231PD 0x80(%R15,%R8,1),%ZMM3,%ZMM22 |
(661) 0x450ce4 VFMADD231PD 0xc0(%R15,%R8,1),%ZMM3,%ZMM23 |
(661) 0x450cec VADDPD %ZMM20,%ZMM0,%ZMM1 |
(661) 0x450cf2 VMULPD 0x40(%R9,%R8,1),%ZMM4,%ZMM0 |
(661) 0x450cfa VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 |
(661) 0x450d01 VFMADD231PD 0x40(%R8,%RAX,1),%ZMM5,%ZMM0 |
(661) 0x450d09 VMOVUPD %ZMM1,(%RCX,%R8,1) |
(661) 0x450d10 VADDPD %ZMM21,%ZMM0,%ZMM1 |
(661) 0x450d16 VMULPD 0x80(%R9,%R8,1),%ZMM4,%ZMM0 |
(661) 0x450d1e VFMADD213PD 0x40(%RCX,%R8,1),%ZMM16,%ZMM1 |
(661) 0x450d26 VFMADD231PD 0x80(%R8,%RAX,1),%ZMM5,%ZMM0 |
(661) 0x450d2e VMOVUPD %ZMM1,0x40(%RCX,%R8,1) |
(661) 0x450d36 VADDPD %ZMM22,%ZMM0,%ZMM1 |
(661) 0x450d3c VMULPD 0xc0(%R9,%R8,1),%ZMM4,%ZMM0 |
(661) 0x450d44 VFMADD213PD 0x80(%RCX,%R8,1),%ZMM16,%ZMM1 |
(661) 0x450d4c VFMADD231PD 0xc0(%R8,%RAX,1),%ZMM5,%ZMM0 |
(661) 0x450d54 VMOVUPD %ZMM1,0x80(%RCX,%R8,1) |
(661) 0x450d5c VADDPD %ZMM23,%ZMM0,%ZMM1 |
(661) 0x450d62 VFMADD213PD 0xc0(%RCX,%R8,1),%ZMM16,%ZMM1 |
(661) 0x450d6a VMOVUPD %ZMM1,0xc0(%RCX,%R8,1) |
(661) 0x450d72 ADD $0x100,%R8 |
(661) 0x450d79 CMP %R13,%R8 |
(661) 0x450d7c JNE 450ca0 |
0x450d82 MOV 0xd0(%RSP),%EDX |
0x450d89 TEST %EDX,%EDX |
0x450d8b JE 450eb0 |
0x450d91 MOV 0xb8(%RSP),%RDX |
0x450d99 MOV %R14,%RSI |
0x450d9c SUB %RDX,%RSI |
0x450d9f LEA -0x1(%RSI),%R9 |
0x450da3 CMP $0x2,%R9 |
0x450da7 JBE 450df9 |
0x450da9 LEA (%RBX,%RDX,1),%R9 |
0x450dad LEA (%RCX,%RDX,8),%R8 |
0x450db1 VBROADCASTSD %XMM6,%YMM0 |
0x450db6 LEA (%RBX,%R9,1),%R10 |
0x450dba LEA (%RBX,%R10,1),%R15 |
0x450dbe VMULPD (%RAX,%R10,8),%YMM11,%YMM1 |
0x450dc4 VMULPD (%RAX,%R15,8),%YMM13,%YMM24 |
0x450dcb VFMADD231PD (%RAX,%R9,8),%YMM12,%YMM1 |
0x450dd1 VFMADD231PD (%RAX,%RDX,8),%YMM14,%YMM24 |
0x450dd8 VADDPD %YMM24,%YMM1,%YMM1 |
0x450dde VFMADD213PD (%R8),%YMM1,%YMM0 |
0x450de3 VMOVUPD %YMM0,(%R8) |
0x450de8 TEST $0x3,%SIL |
0x450dec JE 450eb0 |
0x450df2 AND $-0x4,%RSI |
0x450df6 ADD %RSI,%RDX |
0x450df9 LEA (%RBX,%RDX,1),%R10 |
0x450dfd LEA (,%RDX,8),%R8 |
0x450e05 LEA (%R10,%RBX,1),%RSI |
0x450e09 LEA (%RCX,%R8,1),%R9 |
0x450e0d VMULSD (%RAX,%RSI,8),%XMM7,%XMM0 |
0x450e12 ADD %RBX,%RSI |
0x450e15 LEA 0x1(%RDX),%R15 |
0x450e19 VMULSD (%RAX,%RSI,8),%XMM8,%XMM1 |
0x450e1e VFMADD231SD (%RAX,%R10,8),%XMM10,%XMM0 |
0x450e24 VFMADD231SD (%RAX,%RDX,8),%XMM9,%XMM1 |
0x450e2a VADDSD %XMM1,%XMM0,%XMM0 |
0x450e2e VFMADD213SD (%R9),%XMM6,%XMM0 |
0x450e33 VMOVSD %XMM0,(%R9) |
0x450e38 CMP %R14,%R15 |
0x450e3b JAE 450eb0 |
0x450e3d ADD %RBX,%R15 |
0x450e40 LEA 0x8(%RCX,%R8,1),%R10 |
0x450e45 ADD $0x2,%RDX |
0x450e49 LEA (%RBX,%R15,1),%R9 |
0x450e4d VMULSD (%RAX,%R9,8),%XMM7,%XMM0 |
0x450e53 ADD %RBX,%R9 |
0x450e56 VMULSD (%RAX,%R9,8),%XMM8,%XMM1 |
0x450e5c VFMADD231SD (%RAX,%R15,8),%XMM10,%XMM0 |
0x450e62 VFMADD231SD 0x8(%R8,%RAX,1),%XMM9,%XMM1 |
0x450e69 VADDSD %XMM1,%XMM0,%XMM0 |
0x450e6d VFMADD213SD (%R10),%XMM6,%XMM0 |
0x450e72 VMOVSD %XMM0,(%R10) |
0x450e77 CMP %R14,%RDX |
0x450e7a JAE 450eb0 |
0x450e7c ADD %RBX,%RDX |
0x450e7f LEA 0x10(%RCX,%R8,1),%R15 |
0x450e84 LEA (%RBX,%RDX,1),%RSI |
0x450e88 VMULSD (%RAX,%RSI,8),%XMM7,%XMM0 |
0x450e8d ADD %RBX,%RSI |
0x450e90 VMULSD (%RAX,%RSI,8),%XMM8,%XMM1 |
0x450e95 VFMADD231SD (%RAX,%RDX,8),%XMM10,%XMM0 |
0x450e9b VFMADD231SD 0x10(%R8,%RAX,1),%XMM9,%XMM1 |
0x450ea2 VADDSD %XMM1,%XMM0,%XMM0 |
0x450ea6 VFMADD213SD (%R15),%XMM6,%XMM0 |
0x450eab VMOVSD %XMM0,(%R15) |
0x450eb0 MOV 0xd8(%RSP),%RDX |
0x450eb8 ADD $0x8,%RDI |
0x450ebc ADD %RDX,%RAX |
0x450ebf CMP %RDI,0xc8(%RSP) |
0x450ec7 JNE 450bae |
0x450fc0 XOR %EDX,%EDX |
0x450fc2 JMP 450d99 |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 66 - 74 |
-------------------------------------------------------------------------------- |
66: for (size_t j = 0; j < 4; j++) |
67: { |
68: const T pre00 = a[i] * b[j]; |
69: const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs; |
70: #pragma omp simd aligned(coefs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_) |
71: for (size_t n = 0; n < num_splines; n++) |
72: vals[n] += pre00 * |
73: (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] + |
74: c[3] * coefs[n + 3 * zs]); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:194 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:216 | exec |
○ | main._omp_fn.1 | miniqmc.cpp:486 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.57 |
CQA speedup if FP arith vectorized | 1.11 |
CQA speedup if fully vectorized | 1.38 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.38 |
Bottlenecks | micro-operation queue, |
Function | miniqmcreference::einspline_spo_ref |
Source | MultiBsplineRef.hpp:66-74 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 35.75 |
CQA cycles if no scalar integer | 22.75 |
CQA cycles if FP arith vectorized | 32.27 |
CQA cycles if fully vectorized | 25.84 |
Front-end cycles | 35.75 |
DIV/SQRT cycles | 26.00 |
P0 cycles | 26.00 |
P1 cycles | 20.50 |
P2 cycles | 20.50 |
P3 cycles | 7.00 |
P4 cycles | 26.00 |
P5 cycles | 26.00 |
P6 cycles | 7.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 36.17 |
Stall cycles (UFS) | 0.00 |
Nb insns | 117.00 |
Nb uops | 117.00 |
Nb loads | 41.00 |
Nb stores | 7.00 |
Nb stack references | 5.00 |
FLOP/cycle | 7.83 |
Nb FLOP add-sub | 31.00 |
Nb FLOP mul | 63.00 |
Nb FLOP fma | 93.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 42.85 |
Bytes prefetched | 0.00 |
Bytes loaded | 1284.00 |
Bytes stored | 248.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 45.90 |
Vectorization ratio load | 54.05 |
Vectorization ratio store | 57.14 |
Vectorization ratio mul | 53.33 |
Vectorization ratio add_sub | 57.14 |
Vectorization ratio fma | 57.14 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 46.82 |
Vector-efficiency ratio load | 53.04 |
Vector-efficiency ratio store | 55.36 |
Vector-efficiency ratio mul | 52.50 |
Vector-efficiency ratio add_sub | 55.36 |
Vector-efficiency ratio fma | 55.36 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.93 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.57 |
CQA speedup if FP arith vectorized | 1.11 |
CQA speedup if fully vectorized | 1.38 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.38 |
Bottlenecks | micro-operation queue, |
Function | miniqmcreference::einspline_spo_ref |
Source | MultiBsplineRef.hpp:66-74 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 35.75 |
CQA cycles if no scalar integer | 22.75 |
CQA cycles if FP arith vectorized | 32.27 |
CQA cycles if fully vectorized | 25.84 |
Front-end cycles | 35.75 |
DIV/SQRT cycles | 26.00 |
P0 cycles | 26.00 |
P1 cycles | 20.50 |
P2 cycles | 20.50 |
P3 cycles | 7.00 |
P4 cycles | 26.00 |
P5 cycles | 26.00 |
P6 cycles | 7.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 36.17 |
Stall cycles (UFS) | 0.00 |
Nb insns | 117.00 |
Nb uops | 117.00 |
Nb loads | 41.00 |
Nb stores | 7.00 |
Nb stack references | 5.00 |
FLOP/cycle | 7.83 |
Nb FLOP add-sub | 31.00 |
Nb FLOP mul | 63.00 |
Nb FLOP fma | 93.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 42.85 |
Bytes prefetched | 0.00 |
Bytes loaded | 1284.00 |
Bytes stored | 248.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 45.90 |
Vectorization ratio load | 54.05 |
Vectorization ratio store | 57.14 |
Vectorization ratio mul | 53.33 |
Vectorization ratio add_sub | 57.14 |
Vectorization ratio fma | 57.14 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 46.82 |
Vector-efficiency ratio load | 53.04 |
Vector-efficiency ratio store | 55.36 |
Vector-efficiency ratio mul | 52.50 |
Vector-efficiency ratio add_sub | 55.36 |
Vector-efficiency ratio fma | 55.36 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.93 |
Path / |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:66-74 |
Module | exec |
nb instructions | 117 |
nb uops | 117 |
loop length | 580 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 7 |
used zmm registers | 10 |
nb stack references | 5 |
ADD-SUB / MUL ratio | 0.47 |
micro-operation queue | 35.75 cycles |
front end | 35.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 26.00 | 26.00 | 20.50 | 20.50 | 7.00 | 26.00 | 26.00 | 7.00 |
cycles | 26.00 | 26.00 | 20.50 | 20.50 | 7.00 | 26.00 | 26.00 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 36.17 |
Stall cycles | 0.00 |
Front-end | 35.75 |
Dispatch | 26.00 |
Overall L1 | 35.75 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 53% |
load | 55% |
store | 57% |
mul | 53% |
add-sub | 57% |
fma | 57% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 45% |
load | 54% |
store | 57% |
mul | 53% |
add-sub | 57% |
fma | 57% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 52% |
load | 54% |
store | 55% |
mul | 52% |
add-sub | 55% |
fma | 55% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 46% |
load | 53% |
store | 55% |
mul | 52% |
add-sub | 55% |
fma | 55% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMULSD (%RDI),%XMM15,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMPQ $0x6,0xc0(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JBE 450fc0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x40(%R13),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R12,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM6,%ZMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x6,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA (%R9,%R12,1),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%R15,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x3,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450ca0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x1,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450c63 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x2,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450c2f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMULPD (%R9),%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
MOV $0x40,%R8D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULPD (%R10),%ZMM2,%ZMM17 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%R15),%ZMM3,%ZMM17 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VADDPD %ZMM17,%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%RCX),%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM1,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMULPD (%R10,%R8,1),%ZMM2,%ZMM18 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM18 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VADDPD %ZMM18,%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM1,(%RCX,%R8,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x40,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMULPD (%R10,%R8,1),%ZMM2,%ZMM19 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM19 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VADDPD %ZMM19,%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM1,(%RCX,%R8,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x40,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450d82 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0xd0(%RSP),%EDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %EDX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R14,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 450df9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA (%RBX,%RDX,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RCX,%RDX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM6,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
LEA (%RBX,%R9,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULPD (%RAX,%R10,8),%YMM11,%YMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RAX,%R15,8),%YMM13,%YMM24 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%R9,8),%YMM12,%YMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%RDX,8),%YMM14,%YMM24 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM24,%YMM1,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%R8),%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM0,(%R8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST $0x3,%SIL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
AND $-0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RBX,%RDX,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R10,%RBX,1),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RCX,%R8,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%RSI,8),%XMM7,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x1(%RDX),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%RSI,8),%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%R10,8),%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%RDX,8),%XMM9,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%R9),%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,(%R9) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R14,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %RBX,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x8(%RCX,%R8,1),%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD $0x2,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RBX,%R15,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%R9,8),%XMM7,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RBX,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULSD (%RAX,%R9,8),%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%R15,8),%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x8(%R8,%RAX,1),%XMM9,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%R10),%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R14,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %RBX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x10(%RCX,%R8,1),%R15 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RBX,%RDX,1),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%RSI,8),%XMM7,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULSD (%RAX,%RSI,8),%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%RDX,8),%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x10(%R8,%RAX,1),%XMM9,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%R15),%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,(%R15) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x8,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %RDX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RDI,0xc8(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 450bae | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 450d99 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:66-74 |
Module | exec |
nb instructions | 117 |
nb uops | 117 |
loop length | 580 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 7 |
used zmm registers | 10 |
nb stack references | 5 |
ADD-SUB / MUL ratio | 0.47 |
micro-operation queue | 35.75 cycles |
front end | 35.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 26.00 | 26.00 | 20.50 | 20.50 | 7.00 | 26.00 | 26.00 | 7.00 |
cycles | 26.00 | 26.00 | 20.50 | 20.50 | 7.00 | 26.00 | 26.00 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 36.17 |
Stall cycles | 0.00 |
Front-end | 35.75 |
Dispatch | 26.00 |
Overall L1 | 35.75 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 53% |
load | 55% |
store | 57% |
mul | 53% |
add-sub | 57% |
fma | 57% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 45% |
load | 54% |
store | 57% |
mul | 53% |
add-sub | 57% |
fma | 57% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 52% |
load | 54% |
store | 55% |
mul | 52% |
add-sub | 55% |
fma | 55% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 46% |
load | 53% |
store | 55% |
mul | 52% |
add-sub | 55% |
fma | 55% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMULSD (%RDI),%XMM15,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMPQ $0x6,0xc0(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JBE 450fc0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x40(%R13),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R12,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM6,%ZMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SHR $0x6,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA (%R9,%R12,1),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%R15,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x3,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450ca0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x1,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450c63 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CMP $0x2,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450c2f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMULPD (%R9),%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
MOV $0x40,%R8D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULPD (%R10),%ZMM2,%ZMM17 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%R15),%ZMM3,%ZMM17 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VADDPD %ZMM17,%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%RCX),%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM1,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMULPD (%R10,%R8,1),%ZMM2,%ZMM18 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM18 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VADDPD %ZMM18,%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM1,(%RCX,%R8,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x40,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULPD (%R9,%R8,1),%ZMM4,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMULPD (%R10,%R8,1),%ZMM2,%ZMM19 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%R8,1),%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%R15,%R8,1),%ZMM3,%ZMM19 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VADDPD %ZMM19,%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%RCX,%R8,1),%ZMM16,%ZMM1 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
VMOVUPD %ZMM1,(%RCX,%R8,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x40,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450d82 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0xd0(%RSP),%EDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %EDX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R14,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB %RDX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JBE 450df9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA (%RBX,%RDX,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RCX,%RDX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM6,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
LEA (%RBX,%R9,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULPD (%RAX,%R10,8),%YMM11,%YMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RAX,%R15,8),%YMM13,%YMM24 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%R9,8),%YMM12,%YMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD (%RAX,%RDX,8),%YMM14,%YMM24 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM24,%YMM1,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PD (%R8),%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM0,(%R8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST $0x3,%SIL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
AND $-0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RBX,%RDX,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R10,%RBX,1),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RCX,%R8,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%RSI,8),%XMM7,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x1(%RDX),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%RSI,8),%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%R10,8),%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%RDX,8),%XMM9,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%R9),%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,(%R9) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R14,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %RBX,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x8(%RCX,%R8,1),%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD $0x2,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RBX,%R15,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%R9,8),%XMM7,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RBX,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULSD (%RAX,%R9,8),%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%R15,8),%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x8(%R8,%RAX,1),%XMM9,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%R10),%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R14,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JAE 450eb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
ADD %RBX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x10(%RCX,%R8,1),%R15 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RBX,%RDX,1),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RAX,%RSI,8),%XMM7,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMULSD (%RAX,%RSI,8),%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD (%RAX,%RDX,8),%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x10(%R8,%RAX,1),%XMM9,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%R15),%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,(%R15) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x8,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %RDX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RDI,0xc8(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 450bae | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 450d99 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |