Loop Id: 741 | Module: exec | Source: einspline_spo_ref.hpp:223-227 [...] | Coverage: 0.73% |
---|
Loop Id: 741 | Module: exec | Source: einspline_spo_ref.hpp:223-227 [...] | Coverage: 0.73% |
---|
0x45d38f VMOVSD (%R11,%RAX,1),%XMM14 [10] |
0x45d395 ADD $0x60,%RDX |
0x45d399 VMOVSD %XMM14,(%R10,%RAX,1) [7] |
0x45d39f VMOVSD (%RSI,%RAX,1),%XMM4 [4] |
0x45d3a4 VMOVSD (%RCX,%RAX,1),%XMM15 [2] |
0x45d3a9 VMOVHPD (%R9,%RAX,1),%XMM4,%XMM0 [5] |
0x45d3af VMOVSD %XMM15,-0x50(%RDX) [1] |
0x45d3b4 VMOVUPD %XMM0,-0x60(%RDX) [1] |
0x45d3b9 VMOVSD (%R8,%RAX,1),%XMM2 [6] |
0x45d3bf VMOVSD %XMM2,(%RDI,%RAX,1) [8] |
0x45d3c4 VMOVSD 0x8(%R11,%RAX,1),%XMM1 [10] |
0x45d3cb VMOVSD %XMM1,0x8(%RAX,%R10,1) [9] |
0x45d3d2 VMOVSD 0x8(%RSI,%RAX,1),%XMM5 [4] |
0x45d3d8 VMOVSD 0x8(%RCX,%RAX,1),%XMM3 [2] |
0x45d3de VMOVHPD 0x8(%R9,%RAX,1),%XMM5,%XMM6 [5] |
0x45d3e5 VMOVSD %XMM3,-0x38(%RDX) [1] |
0x45d3ea VMOVUPD %XMM6,-0x48(%RDX) [1] |
0x45d3ef VMOVSD 0x8(%R8,%RAX,1),%XMM7 [6] |
0x45d3f6 VMOVSD %XMM7,0x8(%RAX,%RDI,1) [3] |
0x45d3fc VMOVSD 0x10(%R11,%RAX,1),%XMM8 [10] |
0x45d403 VMOVSD %XMM8,0x10(%RAX,%R10,1) [9] |
0x45d40a VMOVSD 0x10(%RSI,%RAX,1),%XMM10 [4] |
0x45d410 VMOVSD 0x10(%RCX,%RAX,1),%XMM9 [2] |
0x45d416 VMOVHPD 0x10(%R9,%RAX,1),%XMM10,%XMM11 [5] |
0x45d41d VMOVSD %XMM9,-0x20(%RDX) [1] |
0x45d422 VMOVUPD %XMM11,-0x30(%RDX) [1] |
0x45d427 VMOVSD 0x10(%R8,%RAX,1),%XMM12 [6] |
0x45d42e VMOVSD %XMM12,0x10(%RAX,%RDI,1) [3] |
0x45d434 VMOVSD 0x18(%R11,%RAX,1),%XMM13 [10] |
0x45d43b VMOVSD %XMM13,0x18(%RAX,%R10,1) [9] |
0x45d442 VMOVSD 0x18(%RSI,%RAX,1),%XMM15 [4] |
0x45d448 VMOVSD 0x18(%RCX,%RAX,1),%XMM14 [2] |
0x45d44e VMOVHPD 0x18(%R9,%RAX,1),%XMM15,%XMM4 [5] |
0x45d455 VMOVUPD %XMM4,-0x18(%RDX) [1] |
0x45d45a VMOVSD %XMM14,-0x8(%RDX) [1] |
0x45d45f VMOVSD 0x18(%R8,%RAX,1),%XMM0 [6] |
0x45d466 ADD $0x20,%RAX |
0x45d46a VMOVSD %XMM0,-0x8(%RAX,%RDI,1) [11] |
0x45d470 CMP %R12,%RAX |
0x45d473 JNE 45d38f |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183 |
-------------------------------------------------------------------------------- |
183: return (const_cast<T1&>(a) = b); |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227 |
-------------------------------------------------------------------------------- |
223: for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++) |
224: { |
225: psi_v[j] = psi[i][j - first]; |
226: dpsi_v[j] = grad[i][j - first]; |
227: d2psi_v[j] = hess[i].data(0)[j - first]; |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 146 - 146 |
-------------------------------------------------------------------------------- |
146: X[i] = base[i * offset]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►39.44+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:100 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:202 | exec |
○ | main._omp_fn.1 | miniqmc.cpp:438 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►37.32+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:100 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:202 | exec |
○ | main._omp_fn.1 | miniqmc.cpp:438 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►13.38+ | miniqmcreference::DiracDetermi[...] | OhmmsVector.h:144 | exec |
○ | qmcplusplus::WaveFunction::eva[...] | WaveFunction.cpp:177 | exec |
○ | main._omp_fn.0 | miniqmc.cpp:390 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►9.86+ | miniqmcreference::DiracDetermi[...] | OhmmsVector.h:144 | exec |
○ | qmcplusplus::WaveFunction::eva[...] | WaveFunction.cpp:178 | exec |
○ | main._omp_fn.0 | miniqmc.cpp:390 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.40 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.33 |
Bottlenecks | P4, |
Function | miniqmcreference::einspline_spo_ref |
Source | OperatorTags.h:183-183,einspline_spo_ref.hpp:223-227,TinyVector.h:146-146 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 2.50 |
Front-end cycles | 10.75 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 12.00 |
P2 cycles | 12.00 |
P3 cycles | 16.00 |
P4 cycles | 4.00 |
P5 cycles | 1.00 |
P6 cycles | 12.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 16.13 |
Stall cycles (UFS) | 5.01 |
Nb insns | 40.00 |
Nb uops | 39.00 |
Nb loads | 20.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 160.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 5.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 11.11 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 25.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 13.89 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 15.63 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.40 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.33 |
Bottlenecks | P4, |
Function | miniqmcreference::einspline_spo_ref |
Source | OperatorTags.h:183-183,einspline_spo_ref.hpp:223-227,TinyVector.h:146-146 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 2.50 |
Front-end cycles | 10.75 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 12.00 |
P2 cycles | 12.00 |
P3 cycles | 16.00 |
P4 cycles | 4.00 |
P5 cycles | 1.00 |
P6 cycles | 12.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 16.13 |
Stall cycles (UFS) | 5.01 |
Nb insns | 40.00 |
Nb uops | 39.00 |
Nb loads | 20.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 20.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 160.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 5.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 11.11 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 25.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 13.89 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 15.63 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | einspline_spo_ref.hpp:223-227 |
Module | exec |
nb instructions | 40 |
nb uops | 39 |
loop length | 234 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.75 cycles |
front end | 10.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 12.00 | 12.00 | 16.00 | 4.00 | 1.00 | 12.00 |
cycles | 1.00 | 1.00 | 12.00 | 12.00 | 16.00 | 4.00 | 1.00 | 12.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 16.13 |
Stall cycles | 5.01 |
RS full (events) | 0.02 |
LM full (events) | 0.02 |
SB full (events) | 10.47 |
Front-end | 10.75 |
Dispatch | 16.00 |
Data deps. | 1.00 |
Overall L1 | 16.00 |
all | 11% |
load | 0% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 13% |
load | 12% |
store | 15% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R11,%RAX,1),%XMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x60,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM14,(%R10,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD (%RSI,%RAX,1),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RCX,%RAX,1),%XMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD (%R9,%RAX,1),%XMM4,%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVSD %XMM15,-0x50(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM0,-0x60(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD (%R8,%RAX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM2,(%RDI,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x8(%R11,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM1,0x8(%RAX,%R10,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x8(%RSI,%RAX,1),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x8(%RCX,%RAX,1),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD 0x8(%R9,%RAX,1),%XMM5,%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVSD %XMM3,-0x38(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM6,-0x48(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x8(%R8,%RAX,1),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM7,0x8(%RAX,%RDI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x10(%R11,%RAX,1),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM8,0x10(%RAX,%R10,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x10(%RSI,%RAX,1),%XMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x10(%RCX,%RAX,1),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD 0x10(%R9,%RAX,1),%XMM10,%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVSD %XMM9,-0x20(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM11,-0x30(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x10(%R8,%RAX,1),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM12,0x10(%RAX,%RDI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x18(%R11,%RAX,1),%XMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM13,0x18(%RAX,%R10,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x18(%RSI,%RAX,1),%XMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x18(%RCX,%RAX,1),%XMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD 0x18(%R9,%RAX,1),%XMM15,%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVUPD %XMM4,-0x18(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD %XMM14,-0x8(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x18(%R8,%RAX,1),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x20,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM0,-0x8(%RAX,%RDI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R12,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 45d38f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | einspline_spo_ref.hpp:223-227 |
Module | exec |
nb instructions | 40 |
nb uops | 39 |
loop length | 234 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.75 cycles |
front end | 10.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 12.00 | 12.00 | 16.00 | 4.00 | 1.00 | 12.00 |
cycles | 1.00 | 1.00 | 12.00 | 12.00 | 16.00 | 4.00 | 1.00 | 12.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 16.13 |
Stall cycles | 5.01 |
RS full (events) | 0.02 |
LM full (events) | 0.02 |
SB full (events) | 10.47 |
Front-end | 10.75 |
Dispatch | 16.00 |
Data deps. | 1.00 |
Overall L1 | 16.00 |
all | 11% |
load | 0% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 13% |
load | 12% |
store | 15% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R11,%RAX,1),%XMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x60,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM14,(%R10,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD (%RSI,%RAX,1),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RCX,%RAX,1),%XMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD (%R9,%RAX,1),%XMM4,%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVSD %XMM15,-0x50(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM0,-0x60(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD (%R8,%RAX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM2,(%RDI,%RAX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x8(%R11,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM1,0x8(%RAX,%R10,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x8(%RSI,%RAX,1),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x8(%RCX,%RAX,1),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD 0x8(%R9,%RAX,1),%XMM5,%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVSD %XMM3,-0x38(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM6,-0x48(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x8(%R8,%RAX,1),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM7,0x8(%RAX,%RDI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x10(%R11,%RAX,1),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM8,0x10(%RAX,%R10,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x10(%RSI,%RAX,1),%XMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x10(%RCX,%RAX,1),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD 0x10(%R9,%RAX,1),%XMM10,%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVSD %XMM9,-0x20(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %XMM11,-0x30(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x10(%R8,%RAX,1),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM12,0x10(%RAX,%RDI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x18(%R11,%RAX,1),%XMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD %XMM13,0x18(%RAX,%R10,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x18(%RSI,%RAX,1),%XMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x18(%RCX,%RAX,1),%XMM14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVHPD 0x18(%R9,%RAX,1),%XMM15,%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 4 | 1 |
VMOVUPD %XMM4,-0x18(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD %XMM14,-0x8(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x18(%R8,%RAX,1),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD $0x20,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM0,-0x8(%RAX,%RDI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R12,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 45d38f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |