Function: __libm_exp_l9 | Module: exec | Source: :0-0 | Coverage: 0.01% |
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Function: __libm_exp_l9 | Module: exec | Source: :0-0 | Coverage: 0.01% |
---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x47a280 ENDBR64 |
0x47a284 VMOVQ %XMM0,%RAX |
0x47a289 SHR $0x30,%RAX |
0x47a28d AND $0x7fff,%EAX |
0x47a292 LEA -0x4084(%RAX),%ECX |
0x47a298 CMP $-0x404,%ECX |
0x47a29e JB 47a376 |
0x47a2a4 VSTMXCSR -0x4(%RSP) |
0x47a2aa MOV -0x4(%RSP),%ECX |
0x47a2ae MOV %ECX,%EAX |
0x47a2b0 AND $0x6000,%EAX |
0x47a2b5 JE 47a2c7 |
0x47a2b7 AND $-0x6001,%ECX |
0x47a2bd MOV %ECX,-0x8(%RSP) |
0x47a2c1 VLDMXCSR -0x8(%RSP) |
0x47a2c7 VMOVSD 0x39551(%RIP),%XMM1 |
0x47a2cf VFMADD213SD 0x39550(%RIP),%XMM0,%XMM1 |
0x47a2d8 VMOVQ %XMM1,%RCX |
0x47a2dd LEA (%RCX,%RCX,1),%EDX |
0x47a2e0 AND $0x7e,%EDX |
0x47a2e3 AND $0x3ffc0,%ECX |
0x47a2e9 LEA 0x1(%RDX),%ESI |
0x47a2ec VADDSD 0x3953c(%RIP),%XMM1,%XMM1 |
0x47a2f4 VFMADD231SD 0x3953b(%RIP),%XMM1,%XMM0 |
0x47a2fd VFMADD231SD 0x3953a(%RIP),%XMM1,%XMM0 |
0x47a306 VMOVD %ECX,%XMM1 |
0x47a30a VPSLLQ $0x2e,%XMM1,%XMM2 |
0x47a30f VMOVSD 0x39531(%RIP),%XMM3 |
0x47a317 VFMADD213SD 0x39530(%RIP),%XMM0,%XMM3 |
0x47a320 VMOVSD 0x39530(%RIP),%XMM1 |
0x47a328 VFMADD213SD 0x3952f(%RIP),%XMM0,%XMM1 |
0x47a331 VMULSD %XMM0,%XMM0,%XMM4 |
0x47a335 LEA 0x39534(%RIP),%RCX |
0x47a33c VMOVQ (%RCX,%RDX,8),%XMM5 |
0x47a341 VPOR %XMM5,%XMM2,%XMM2 |
0x47a345 VADDSD (%RCX,%RSI,8),%XMM0,%XMM0 |
0x47a34a VFMADD231SD %XMM3,%XMM4,%XMM1 |
0x47a34f VFMADD213SD %XMM0,%XMM4,%XMM1 |
0x47a354 VFMADD132SD %XMM2,%XMM2,%XMM1 |
0x47a359 TEST %EAX,%EAX |
0x47a35b JE 47a385 |
0x47a35d VSTMXCSR -0xc(%RSP) |
0x47a363 OR -0xc(%RSP),%EAX |
0x47a367 MOV %EAX,-0x10(%RSP) |
0x47a36b VLDMXCSR -0x10(%RSP) |
0x47a371 VMOVAPD %XMM1,%XMM0 |
0x47a375 RET |
0x47a376 CMP $0x3c7f,%EAX |
0x47a37b JA 47a38a |
0x47a37d VADDSD 0x13ca3(%RIP),%XMM0,%XMM1 |
0x47a385 VMOVAPD %XMM1,%XMM0 |
0x47a389 RET |
0x47a38a JMP 474060 |
0x47a38f NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | main.extracted.104 | stl_vector.h:1126 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | main | miniqmc.cpp:404 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 54 |
nb uops | 63 |
loop length | 272 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
ADD-SUB / MUL ratio | 3.00 |
micro-operation queue | 16.00 cycles |
front end | 16.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 12.00 | 12.00 | 8.00 | 8.00 | 4.00 | 12.00 | 12.00 | 6.00 |
cycles | 12.00 | 12.00 | 8.00 | 8.00 | 4.00 | 12.00 | 12.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 37.37 |
Stall cycles | 21.38 |
RS full (events) | 35.70 |
Front-end | 16.00 |
Dispatch | 12.00 |
Overall L1 | 16.00 |
all | 20% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 28% |
all | 11% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 14% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 44% |
all | 11% |
load | 12% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 13% |
load | 12% |
store | 6% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||
VMOVQ %XMM0,%RAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SHR $0x30,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
AND $0x7fff,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x4084(%RAX),%ECX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $-0x404,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 47a376 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VSTMXCSR -0x4(%RSP) | 3 | 1 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 10 | 1 |
MOV -0x4(%RSP),%ECX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $0x6000,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 47a2c7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
AND $-0x6001,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %ECX,-0x8(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VLDMXCSR -0x8(%RSP) | 4 | 1 | 0 | 0.50 | 0.50 | 0 | 1 | 1 | 0 | 5 | 3 |
VMOVSD 0x39551(%RIP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SD 0x39550(%RIP),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVQ %XMM1,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LEA (%RCX,%RCX,1),%EDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x7e,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
AND $0x3ffc0,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x1(%RDX),%ESI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSD 0x3953c(%RIP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x3953b(%RIP),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x3953a(%RIP),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVD %ECX,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 2 | 1 |
VPSLLQ $0x2e,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x39531(%RIP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SD 0x39530(%RIP),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x39530(%RIP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SD 0x3952f(%RIP),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x39534(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVQ (%RCX,%RDX,8),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VPOR %XMM5,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDSD (%RCX,%RSI,8),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD %XMM3,%XMM4,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD %XMM0,%XMM4,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD %XMM2,%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 47a385 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VSTMXCSR -0xc(%RSP) | 3 | 1 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 10 | 1 |
OR -0xc(%RSP),%EAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %EAX,-0x10(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VLDMXCSR -0x10(%RSP) | 4 | 1 | 0 | 0.50 | 0.50 | 0 | 1 | 1 | 0 | 5 | 3 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
CMP $0x3c7f,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JA 47a38a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VADDSD 0x13ca3(%RIP),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
JMP 474060 <__libm_exp_e7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | |
Module | exec |
nb instructions | 54 |
nb uops | 63 |
loop length | 272 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
ADD-SUB / MUL ratio | 3.00 |
micro-operation queue | 16.00 cycles |
front end | 16.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 12.00 | 12.00 | 8.00 | 8.00 | 4.00 | 12.00 | 12.00 | 6.00 |
cycles | 12.00 | 12.00 | 8.00 | 8.00 | 4.00 | 12.00 | 12.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 37.37 |
Stall cycles | 21.38 |
RS full (events) | 35.70 |
Front-end | 16.00 |
Dispatch | 12.00 |
Overall L1 | 16.00 |
all | 20% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 28% |
all | 11% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 14% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 44% |
all | 11% |
load | 12% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 13% |
load | 12% |
store | 6% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||
VMOVQ %XMM0,%RAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SHR $0x30,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
AND $0x7fff,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x4084(%RAX),%ECX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $-0x404,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JB 47a376 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VSTMXCSR -0x4(%RSP) | 3 | 1 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 10 | 1 |
MOV -0x4(%RSP),%ECX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $0x6000,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 47a2c7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
AND $-0x6001,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %ECX,-0x8(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VLDMXCSR -0x8(%RSP) | 4 | 1 | 0 | 0.50 | 0.50 | 0 | 1 | 1 | 0 | 5 | 3 |
VMOVSD 0x39551(%RIP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SD 0x39550(%RIP),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVQ %XMM1,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LEA (%RCX,%RCX,1),%EDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x7e,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
AND $0x3ffc0,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA 0x1(%RDX),%ESI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSD 0x3953c(%RIP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x3953b(%RIP),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x3953a(%RIP),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVD %ECX,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 2 | 1 |
VPSLLQ $0x2e,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x39531(%RIP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SD 0x39530(%RIP),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x39530(%RIP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SD 0x3952f(%RIP),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x39534(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVQ (%RCX,%RDX,8),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VPOR %XMM5,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDSD (%RCX,%RSI,8),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD %XMM3,%XMM4,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD %XMM0,%XMM4,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD %XMM2,%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 47a385 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VSTMXCSR -0xc(%RSP) | 3 | 1 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 10 | 1 |
OR -0xc(%RSP),%EAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %EAX,-0x10(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VLDMXCSR -0x10(%RSP) | 4 | 1 | 0 | 0.50 | 0.50 | 0 | 1 | 1 | 0 | 5 | 3 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
CMP $0x3c7f,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JA 47a38a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VADDSD 0x13ca3(%RIP),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
JMP 474060 <__libm_exp_e7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
○__libm_exp_l9 | 0.01 | 0 |