Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ... | Module: exec | Source: einspline_spo_ref.hpp:203-230 [...] | Coverage: 0.74% |
---|
Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ... | Module: exec | Source: einspline_spo_ref.hpp:203-230 [...] | Coverage: 0.74% |
---|
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 217 - 217 |
-------------------------------------------------------------------------------- |
217: inline const PosType& activeR(int iat) const { return (activePtcl == iat) ? activePos : R[iat]; } |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 183 - 183 |
-------------------------------------------------------------------------------- |
183: return (const_cast<T1&>(a) = b); |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 191 - 194 |
-------------------------------------------------------------------------------- |
191: if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0) |
192: val_dot[i] = T1(0.0); |
193: else |
194: val_dot[i] -= std::floor(val_dot[i]); |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229 |
-------------------------------------------------------------------------------- |
223: return X[i]; |
[...] |
229: return X[i]; |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 203 - 230 |
-------------------------------------------------------------------------------- |
203: ScopedTimer local_timer(timer); |
204: |
205: auto u = Lattice.toUnit_floor(P.activeR(iat)); |
206: for (int i = 0; i < nBlocks; ++i) |
207: MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(), |
208: nSplinesPerBlock); |
209: } |
210: |
211: inline void evaluate(const ParticleSet& P, |
[...] |
219: for (int i = 0; i < nBlocks; ++i) |
220: { |
221: // in real simulation, phase needs to be applied. Here just fake computation |
222: const int first = i * nBlocks; |
223: for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++) |
224: { |
225: psi_v[j] = psi[i][j - first]; |
226: dpsi_v[j] = grad[i][j - first]; |
227: d2psi_v[j] = hess[i].data(0)[j - first]; |
228: } |
229: } |
230: } |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249 |
-------------------------------------------------------------------------------- |
242: ScopeGuard(TIMER& t) : timer(t) { timer.start(); } |
[...] |
249: ~ScopeGuard() { timer.stop(); } |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152 |
-------------------------------------------------------------------------------- |
150: return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6], |
151: lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7], |
152: lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]); |
/usr/include/c++/13.1.1/bits/stl_vector.h: 1126 - 1258 |
-------------------------------------------------------------------------------- |
1126: return *(this->_M_impl._M_start + __n); |
[...] |
1258: { return _M_data_ptr(this->_M_impl._M_start); } |
/usr/include/c++/13.1.1/bits/stl_algobase.h: 238 - 238 |
-------------------------------------------------------------------------------- |
238: if (__b < __a) |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 146 - 146 |
-------------------------------------------------------------------------------- |
146: X[i] = base[i * offset]; |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 237 - 241 |
-------------------------------------------------------------------------------- |
237: T* data() { return myData; } |
238: ///return the base |
239: const T* data() const { return myData; } |
240: ///return the pointer of the i-th components |
241: T* restrict data(size_t i) { return myData + i * nGhosts; } |
0x45cfc0 PUSH %RBP |
0x45cfc1 MOV %RSP,%RBP |
0x45cfc4 PUSH %R15 |
0x45cfc6 PUSH %R14 |
0x45cfc8 MOVSXD %EDX,%R14 |
0x45cfcb PUSH %R13 |
0x45cfcd MOV %RSI,%R13 |
0x45cfd0 PUSH %R12 |
0x45cfd2 PUSH %RBX |
0x45cfd3 MOV %RDI,%RBX |
0x45cfd6 SUB $0x68,%RSP |
0x45cfda MOV %RCX,-0x78(%RBP) |
0x45cfde MOV 0x348(%RDI),%R12 |
0x45cfe5 MOV %R8,-0x80(%RBP) |
0x45cfe9 MOV %R9,-0x88(%RBP) |
0x45cff0 MOV %R12,%RDI |
0x45cff3 CALL 4a40e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv> |
0x45cff8 LEA 0x988(%R13),%RCX |
0x45cfff CMP 0x984(%R13),%R14D |
0x45d006 JE 45d017 |
0x45d008 MOV 0x5e8(%R13),%RAX |
0x45d00f LEA (%R14,%R14,2),%RDX |
0x45d013 LEA (%RAX,%RDX,8),%RCX |
0x45d017 VMOVSD 0x8(%RCX),%XMM4 |
0x45d01c VMOVSD (%RCX),%XMM0 |
0x45d020 VMOVSD 0x10(%RCX),%XMM1 |
0x45d025 VMULSD 0xf8(%RBX),%XMM4,%XMM2 |
0x45d02d VMULSD 0xf0(%RBX),%XMM4,%XMM3 |
0x45d035 VMULSD 0xe8(%RBX),%XMM4,%XMM5 |
0x45d03d VFMADD231SD 0xe0(%RBX),%XMM0,%XMM2 |
0x45d046 VFMADD231SD 0xd8(%RBX),%XMM0,%XMM3 |
0x45d04f VFMADD132SD 0xd0(%RBX),%XMM5,%XMM0 |
0x45d058 VFMADD231SD 0x110(%RBX),%XMM1,%XMM2 |
0x45d061 VFMADD231SD 0x108(%RBX),%XMM1,%XMM3 |
0x45d06a VFMADD132SD 0x100(%RBX),%XMM0,%XMM1 |
0x45d073 VCOMISD 0x72ea5(%RIP),%XMM1 |
0x45d07b JBE 45d08b |
0x45d07d XOR %R15D,%R15D |
0x45d080 VMOVQ %R15,%XMM6 |
0x45d085 VCOMISD %XMM1,%XMM6 |
0x45d089 JA 45d09b |
0x45d08b VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM7 |
0x45d092 VSUBSD %XMM7,%XMM1,%XMM8 |
0x45d096 VMOVQ %XMM8,%R15 |
0x45d09b VCOMISD 0x72e7d(%RIP),%XMM3 |
0x45d0a3 JBE 45d0b2 |
0x45d0a5 XOR %ESI,%ESI |
0x45d0a7 VMOVQ %RSI,%XMM9 |
0x45d0ac VCOMISD %XMM3,%XMM9 |
0x45d0b0 JA 45d0c3 |
0x45d0b2 VRNDSCALESD $0x9,%XMM3,%XMM3,%XMM10 |
0x45d0b9 VSUBSD %XMM10,%XMM3,%XMM11 |
0x45d0be VMOVQ %XMM11,%RSI |
0x45d0c3 VCOMISD 0x72e55(%RIP),%XMM2 |
0x45d0cb JBE 45d0d8 |
0x45d0cd VXORPD %XMM14,%XMM14,%XMM14 |
0x45d0d2 VCOMISD %XMM2,%XMM14 |
0x45d0d6 JA 45d0e4 |
0x45d0d8 VRNDSCALESD $0x9,%XMM2,%XMM2,%XMM13 |
0x45d0df VSUBSD %XMM13,%XMM2,%XMM14 |
0x45d0e4 MOV 0x30(%RBX),%R9D |
0x45d0e8 XOR %R13D,%R13D |
0x45d0eb VMOVQ %RSI,%XMM1 |
0x45d0f0 VMOVSD %XMM14,%XMM14,%XMM2 |
0x45d0f4 TEST %R9D,%R9D |
0x45d0f7 JLE 45d1d8 |
(742) 0x45d0fd MOV 0x300(%RBX),%R14 |
(742) 0x45d104 MOV 0x330(%RBX),%R8 |
(742) 0x45d10b LEA (%R13,%R13,2),%R11 |
(742) 0x45d110 LEA (%R13,%R13,4),%RDI |
(742) 0x45d115 MOV 0x318(%RBX),%R10 |
(742) 0x45d11c MOV 0x2e8(%RBX),%R9 |
(742) 0x45d123 SAL $0x3,%RDI |
(742) 0x45d127 VMOVQ %R15,%XMM0 |
(742) 0x45d12c LEA (%R14,%R11,8),%RAX |
(742) 0x45d130 MOV 0x18(%R8,%RDI,1),%RCX |
(742) 0x45d135 MOVSXD 0x40(%RBX),%R8 |
(742) 0x45d139 VMOVSD %XMM2,-0x40(%RBP) |
(742) 0x45d13e MOV 0x18(%R10,%RDI,1),%RDX |
(742) 0x45d143 MOV (%RAX),%RSI |
(742) 0x45d146 VMOVSD %XMM1,-0x38(%RBP) |
(742) 0x45d14b MOV (%R9,%R13,8),%RDI |
(742) 0x45d14f CALL 45b530 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m> |
(742) 0x45d154 LEA 0x1(%R13),%R8 |
(742) 0x45d158 VMOVSD -0x38(%RBP),%XMM1 |
(742) 0x45d15d VMOVSD -0x40(%RBP),%XMM2 |
(742) 0x45d162 CMP %R8D,0x30(%RBX) |
(742) 0x45d166 JLE 45d1d8 |
(742) 0x45d168 MOV 0x318(%RBX),%RSI |
(742) 0x45d16f MOV 0x300(%RBX),%RDI |
(742) 0x45d176 LEA (%R8,%R8,4),%RDX |
(742) 0x45d17a LEA (%R8,%R8,2),%R11 |
(742) 0x45d17e SAL $0x3,%RDX |
(742) 0x45d182 MOV 0x330(%RBX),%RCX |
(742) 0x45d189 MOV 0x2e8(%RBX),%RAX |
(742) 0x45d190 VMOVQ %R15,%XMM0 |
(742) 0x45d195 MOV 0x18(%RSI,%RDX,1),%R10 |
(742) 0x45d19a LEA (%RDI,%R11,8),%R14 |
(742) 0x45d19e ADD $0x2,%R13 |
(742) 0x45d1a2 VMOVSD %XMM2,-0x40(%RBP) |
(742) 0x45d1a7 MOV 0x18(%RCX,%RDX,1),%RCX |
(742) 0x45d1ac MOV (%RAX,%R8,8),%RDI |
(742) 0x45d1b0 VMOVSD %XMM1,-0x38(%RBP) |
(742) 0x45d1b5 MOV (%R14),%RSI |
(742) 0x45d1b8 MOVSXD 0x40(%RBX),%R8 |
(742) 0x45d1bc MOV %R10,%RDX |
(742) 0x45d1bf CALL 45b530 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m> |
(742) 0x45d1c4 CMP %R13D,0x30(%RBX) |
(742) 0x45d1c8 VMOVSD -0x38(%RBP),%XMM1 |
(742) 0x45d1cd VMOVSD -0x40(%RBP),%XMM2 |
(742) 0x45d1d2 JG 45d0fd |
0x45d1d8 MOV %R12,%RDI |
0x45d1db CALL 4a4310 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv> |
0x45d1e0 MOV 0x30(%RBX),%R12D |
0x45d1e4 MOV %R12D,-0x54(%RBP) |
0x45d1e8 TEST %R12D,%R12D |
0x45d1eb JLE 45d4aa |
0x45d1f1 MOVSXD -0x54(%RBP),%R9 |
0x45d1f5 MOV 0x40(%RBX),%R13D |
0x45d1f9 MOVQ $0,-0x48(%RBP) |
0x45d201 XOR %R14D,%R14D |
0x45d204 MOV 0x8(%RBX),%R15D |
0x45d208 MOVQ $0,-0x50(%RBP) |
0x45d210 LEA (%R9,%R9,2),%RDX |
0x45d214 LEA (,%R9,8),%R8 |
0x45d21c MOV %R13D,-0x58(%RBP) |
0x45d220 SAL $0x3,%RDX |
0x45d224 MOV %R8,-0x60(%RBP) |
0x45d228 MOV %RDX,-0x70(%RBP) |
0x45d22c MOV %R13D,-0x40(%RBP) |
0x45d230 MOVL $0,-0x38(%RBP) |
0x45d237 MOV %R15D,-0x64(%RBP) |
0x45d23b XOR %R15D,%R15D |
0x45d23e XCHG %AX,%AX |
(740) 0x45d240 MOV -0x40(%RBP),%ECX |
(740) 0x45d243 MOV -0x64(%RBP),%R12D |
(740) 0x45d247 CMP %R12D,%ECX |
(740) 0x45d24a CMOVLE %ECX,%R12D |
(740) 0x45d24e CMP %R12D,-0x38(%RBP) |
(740) 0x45d252 JGE 45d479 |
(740) 0x45d258 MOV 0x300(%RBX),%R10 |
(740) 0x45d25f MOV 0x330(%RBX),%RDI |
(740) 0x45d266 MOV -0x80(%RBP),%R13 |
(740) 0x45d26a MOV -0x38(%RBP),%R9D |
(740) 0x45d26e MOV (%R10,%R14,1),%R11 |
(740) 0x45d272 MOV -0x48(%RBP),%RDX |
(740) 0x45d276 MOV -0x78(%RBP),%R10 |
(740) 0x45d27a MOV 0x318(%RBX),%RAX |
(740) 0x45d281 SUB %R9D,%R12D |
(740) 0x45d284 MOV 0x18(%RDI,%R15,1),%R8 |
(740) 0x45d289 ADD 0x18(%R13),%RDX |
(740) 0x45d28d SAL $0x3,%R12 |
(740) 0x45d291 MOV -0x50(%RBP),%RDI |
(740) 0x45d295 MOV -0x88(%RBP),%R13 |
(740) 0x45d29c ADD %R15,%RAX |
(740) 0x45d29f MOV 0x18(%R10),%R10 |
(740) 0x45d2a3 MOV 0x18(%RAX),%RSI |
(740) 0x45d2a7 MOVSXD 0x8(%RAX),%RCX |
(740) 0x45d2ab XOR %EAX,%EAX |
(740) 0x45d2ad ADD %RDI,%R10 |
(740) 0x45d2b0 ADD 0x18(%R13),%RDI |
(740) 0x45d2b4 LEA -0x8(%R12),%R13 |
(740) 0x45d2b9 SHR $0x3,%R13 |
(740) 0x45d2bd LEA (%RSI,%RCX,8),%R9 |
(740) 0x45d2c1 SAL $0x4,%RCX |
(740) 0x45d2c5 INC %R13 |
(740) 0x45d2c8 ADD %RSI,%RCX |
(740) 0x45d2cb AND $0x3,%R13D |
(740) 0x45d2cf JE 45d38f |
(740) 0x45d2d5 CMP $0x1,%R13 |
(740) 0x45d2d9 JE 45d34d |
(740) 0x45d2db CMP $0x2,%R13 |
(740) 0x45d2df JE 45d314 |
(740) 0x45d2e1 VMOVSD (%R11),%XMM15 |
(740) 0x45d2e6 ADD $0x18,%RDX |
(740) 0x45d2ea MOV $0x8,%EAX |
(740) 0x45d2ef VMOVSD %XMM15,(%R10) |
(740) 0x45d2f4 VMOVSD (%RSI),%XMM0 |
(740) 0x45d2f8 VMOVSD (%RCX),%XMM4 |
(740) 0x45d2fc VMOVHPD (%R9),%XMM0,%XMM2 |
(740) 0x45d301 VMOVSD %XMM4,-0x8(%RDX) |
(740) 0x45d306 VMOVUPD %XMM2,-0x18(%RDX) |
(740) 0x45d30b VMOVSD (%R8),%XMM1 |
(740) 0x45d310 VMOVSD %XMM1,(%RDI) |
(740) 0x45d314 VMOVSD (%R11,%RAX,1),%XMM3 |
(740) 0x45d31a ADD $0x18,%RDX |
(740) 0x45d31e VMOVSD %XMM3,(%R10,%RAX,1) |
(740) 0x45d324 VMOVSD (%RSI,%RAX,1),%XMM6 |
(740) 0x45d329 VMOVSD (%RCX,%RAX,1),%XMM5 |
(740) 0x45d32e VMOVHPD (%R9,%RAX,1),%XMM6,%XMM7 |
(740) 0x45d334 VMOVSD %XMM5,-0x8(%RDX) |
(740) 0x45d339 VMOVUPD %XMM7,-0x18(%RDX) |
(740) 0x45d33e VMOVSD (%R8,%RAX,1),%XMM8 |
(740) 0x45d344 VMOVSD %XMM8,(%RDI,%RAX,1) |
(740) 0x45d349 ADD $0x8,%RAX |
(740) 0x45d34d VMOVSD (%R11,%RAX,1),%XMM9 |
(740) 0x45d353 ADD $0x18,%RDX |
(740) 0x45d357 VMOVSD %XMM9,(%R10,%RAX,1) |
(740) 0x45d35d VMOVSD (%RSI,%RAX,1),%XMM11 |
(740) 0x45d362 VMOVSD (%RCX,%RAX,1),%XMM10 |
(740) 0x45d367 VMOVHPD (%R9,%RAX,1),%XMM11,%XMM12 |
(740) 0x45d36d VMOVSD %XMM10,-0x8(%RDX) |
(740) 0x45d372 VMOVUPD %XMM12,-0x18(%RDX) |
(740) 0x45d377 VMOVSD (%R8,%RAX,1),%XMM13 |
(740) 0x45d37d VMOVSD %XMM13,(%RDI,%RAX,1) |
(740) 0x45d382 ADD $0x8,%RAX |
(740) 0x45d386 CMP %R12,%RAX |
(740) 0x45d389 JE 45d479 |
(741) 0x45d38f VMOVSD (%R11,%RAX,1),%XMM14 |
(741) 0x45d395 ADD $0x60,%RDX |
(741) 0x45d399 VMOVSD %XMM14,(%R10,%RAX,1) |
(741) 0x45d39f VMOVSD (%RSI,%RAX,1),%XMM4 |
(741) 0x45d3a4 VMOVSD (%RCX,%RAX,1),%XMM15 |
(741) 0x45d3a9 VMOVHPD (%R9,%RAX,1),%XMM4,%XMM0 |
(741) 0x45d3af VMOVSD %XMM15,-0x50(%RDX) |
(741) 0x45d3b4 VMOVUPD %XMM0,-0x60(%RDX) |
(741) 0x45d3b9 VMOVSD (%R8,%RAX,1),%XMM2 |
(741) 0x45d3bf VMOVSD %XMM2,(%RDI,%RAX,1) |
(741) 0x45d3c4 VMOVSD 0x8(%R11,%RAX,1),%XMM1 |
(741) 0x45d3cb VMOVSD %XMM1,0x8(%RAX,%R10,1) |
(741) 0x45d3d2 VMOVSD 0x8(%RSI,%RAX,1),%XMM5 |
(741) 0x45d3d8 VMOVSD 0x8(%RCX,%RAX,1),%XMM3 |
(741) 0x45d3de VMOVHPD 0x8(%R9,%RAX,1),%XMM5,%XMM6 |
(741) 0x45d3e5 VMOVSD %XMM3,-0x38(%RDX) |
(741) 0x45d3ea VMOVUPD %XMM6,-0x48(%RDX) |
(741) 0x45d3ef VMOVSD 0x8(%R8,%RAX,1),%XMM7 |
(741) 0x45d3f6 VMOVSD %XMM7,0x8(%RAX,%RDI,1) |
(741) 0x45d3fc VMOVSD 0x10(%R11,%RAX,1),%XMM8 |
(741) 0x45d403 VMOVSD %XMM8,0x10(%RAX,%R10,1) |
(741) 0x45d40a VMOVSD 0x10(%RSI,%RAX,1),%XMM10 |
(741) 0x45d410 VMOVSD 0x10(%RCX,%RAX,1),%XMM9 |
(741) 0x45d416 VMOVHPD 0x10(%R9,%RAX,1),%XMM10,%XMM11 |
(741) 0x45d41d VMOVSD %XMM9,-0x20(%RDX) |
(741) 0x45d422 VMOVUPD %XMM11,-0x30(%RDX) |
(741) 0x45d427 VMOVSD 0x10(%R8,%RAX,1),%XMM12 |
(741) 0x45d42e VMOVSD %XMM12,0x10(%RAX,%RDI,1) |
(741) 0x45d434 VMOVSD 0x18(%R11,%RAX,1),%XMM13 |
(741) 0x45d43b VMOVSD %XMM13,0x18(%RAX,%R10,1) |
(741) 0x45d442 VMOVSD 0x18(%RSI,%RAX,1),%XMM15 |
(741) 0x45d448 VMOVSD 0x18(%RCX,%RAX,1),%XMM14 |
(741) 0x45d44e VMOVHPD 0x18(%R9,%RAX,1),%XMM15,%XMM4 |
(741) 0x45d455 VMOVUPD %XMM4,-0x18(%RDX) |
(741) 0x45d45a VMOVSD %XMM14,-0x8(%RDX) |
(741) 0x45d45f VMOVSD 0x18(%R8,%RAX,1),%XMM0 |
(741) 0x45d466 ADD $0x20,%RAX |
(741) 0x45d46a VMOVSD %XMM0,-0x8(%RAX,%RDI,1) |
(741) 0x45d470 CMP %R12,%RAX |
(741) 0x45d473 JNE 45d38f |
(740) 0x45d479 MOV -0x58(%RBP),%R12D |
(740) 0x45d47d MOV -0x54(%RBP),%R11D |
(740) 0x45d481 ADD $0x18,%R14 |
(740) 0x45d485 ADD $0x28,%R15 |
(740) 0x45d489 MOV -0x60(%RBP),%RSI |
(740) 0x45d48d MOV -0x70(%RBP),%R8 |
(740) 0x45d491 ADD %R12D,-0x40(%RBP) |
(740) 0x45d495 ADD %R11D,-0x38(%RBP) |
(740) 0x45d499 ADD %RSI,-0x50(%RBP) |
(740) 0x45d49d ADD %R8,-0x48(%RBP) |
(740) 0x45d4a1 CMP %R14,%R8 |
(740) 0x45d4a4 JNE 45d240 |
0x45d4aa ADD $0x68,%RSP |
0x45d4ae POP %RBX |
0x45d4af POP %R12 |
0x45d4b1 POP %R13 |
0x45d4b3 POP %R14 |
0x45d4b5 POP %R15 |
0x45d4b7 POP %RBP |
0x45d4b8 RET |
0x45d4b9 NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►40.28+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:100 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:202 | exec |
○ | main._omp_fn.1 | miniqmc.cpp:438 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►36.81+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:100 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:202 | exec |
○ | main._omp_fn.1 | miniqmc.cpp:438 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►13.19+ | miniqmcreference::DiracDetermi[...] | OhmmsVector.h:144 | exec |
○ | qmcplusplus::WaveFunction::eva[...] | WaveFunction.cpp:177 | exec |
○ | main._omp_fn.0 | miniqmc.cpp:390 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
►9.72+ | miniqmcreference::DiracDetermi[...] | OhmmsVector.h:144 | exec |
○ | qmcplusplus::WaveFunction::eva[...] | WaveFunction.cpp:178 | exec |
○ | main._omp_fn.0 | miniqmc.cpp:390 | exec |
○ | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | einspline_spo_ref.hpp:203-230 |
Module | exec |
nb instructions | 98 |
nb uops | 106 |
loop length | 443 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 14 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 12 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 26.50 cycles |
front end | 26.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 14.50 | 14.50 | 16.83 | 16.50 | 20.00 | 12.00 | 13.00 | 16.67 |
cycles | 14.50 | 14.50 | 16.83 | 16.50 | 20.00 | 12.00 | 13.00 | 16.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 46.78 |
Stall cycles | 20.23 |
ROB full (events) | 21.71 |
RS full (events) | 2.57 |
Front-end | 26.50 |
Dispatch | 20.00 |
Overall L1 | 26.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 4% |
all | 8% |
load | 7% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
all | 10% |
load | 11% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVSXD %EDX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB $0x68,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,-0x78(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x348(%RDI),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R8,-0x80(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R9,-0x88(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 4a40e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
LEA 0x988(%R13),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x984(%R13),%R14D | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 45d017 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x5e8(%R13),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%R14,%R14,2),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x8(%RCX),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RCX),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x10(%RCX),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0xf8(%RBX),%XMM4,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0xf0(%RBX),%XMM4,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0xe8(%RBX),%XMM4,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0xe0(%RBX),%XMM0,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0xd8(%RBX),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD 0xd0(%RBX),%XMM5,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x110(%RBX),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x108(%RBX),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD 0x100(%RBX),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCOMISD 0x72ea5(%RIP),%XMM1 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 45d08b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVQ %R15,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VCOMISD %XMM1,%XMM6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JA 45d09b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM7 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBSD %XMM7,%XMM1,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVQ %XMM8,%R15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VCOMISD 0x72e7d(%RIP),%XMM3 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 45d0b2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVQ %RSI,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VCOMISD %XMM3,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JA 45d0c3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VRNDSCALESD $0x9,%XMM3,%XMM3,%XMM10 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBSD %XMM10,%XMM3,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVQ %XMM11,%RSI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VCOMISD 0x72e55(%RIP),%XMM2 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 45d0d8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCOMISD %XMM2,%XMM14 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JA 45d0e4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VRNDSCALESD $0x9,%XMM2,%XMM2,%XMM13 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBSD %XMM13,%XMM2,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x30(%RBX),%R9D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVQ %RSI,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM14,%XMM14,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
TEST %R9D,%R9D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 45d1d8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 4a4310 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV 0x30(%RBX),%R12D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R12D,-0x54(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST %R12D,%R12D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 45d4aa | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOVSXD -0x54(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x40(%RBX),%R13D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVQ $0,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x8(%RBX),%R15D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVQ $0,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
LEA (%R9,%R9,2),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R9,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13D,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %R8,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R13D,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVL $0,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV %R15D,-0x64(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x68,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | einspline_spo_ref.hpp:203-230 |
Module | exec |
nb instructions | 98 |
nb uops | 106 |
loop length | 443 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 14 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 12 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 26.50 cycles |
front end | 26.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 14.50 | 14.50 | 16.83 | 16.50 | 20.00 | 12.00 | 13.00 | 16.67 |
cycles | 14.50 | 14.50 | 16.83 | 16.50 | 20.00 | 12.00 | 13.00 | 16.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 46.78 |
Stall cycles | 20.23 |
ROB full (events) | 21.71 |
RS full (events) | 2.57 |
Front-end | 26.50 |
Dispatch | 20.00 |
Overall L1 | 26.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 4% |
all | 8% |
load | 7% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
all | 10% |
load | 11% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVSXD %EDX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SUB $0x68,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,-0x78(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x348(%RDI),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R8,-0x80(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R9,-0x88(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 4a40e0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
LEA 0x988(%R13),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP 0x984(%R13),%R14D | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 45d017 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x5e8(%R13),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%R14,%R14,2),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x8(%RCX),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RCX),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x10(%RCX),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0xf8(%RBX),%XMM4,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0xf0(%RBX),%XMM4,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0xe8(%RBX),%XMM4,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0xe0(%RBX),%XMM0,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0xd8(%RBX),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD 0xd0(%RBX),%XMM5,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x110(%RBX),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x108(%RBX),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD 0x100(%RBX),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCOMISD 0x72ea5(%RIP),%XMM1 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 45d08b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVQ %R15,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VCOMISD %XMM1,%XMM6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JA 45d09b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VRNDSCALESD $0x9,%XMM1,%XMM1,%XMM7 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBSD %XMM7,%XMM1,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVQ %XMM8,%R15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VCOMISD 0x72e7d(%RIP),%XMM3 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 45d0b2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVQ %RSI,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VCOMISD %XMM3,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JA 45d0c3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VRNDSCALESD $0x9,%XMM3,%XMM3,%XMM10 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBSD %XMM10,%XMM3,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVQ %XMM11,%RSI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VCOMISD 0x72e55(%RIP),%XMM2 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 45d0d8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCOMISD %XMM2,%XMM14 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JA 45d0e4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VRNDSCALESD $0x9,%XMM2,%XMM2,%XMM13 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBSD %XMM13,%XMM2,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x30(%RBX),%R9D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVQ %RSI,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM14,%XMM14,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
TEST %R9D,%R9D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 45d1d8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 4a4310 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV 0x30(%RBX),%R12D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %R12D,-0x54(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST %R12D,%R12D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 45d4aa | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOVSXD -0x54(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x40(%RBX),%R13D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVQ $0,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x8(%RBX),%R15D | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVQ $0,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
LEA (%R9,%R9,2),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R9,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13D,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %R8,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %R13D,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVL $0,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
MOV %R15D,-0x64(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x68,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼miniqmcreference::einspline_spo_ref | 0.74 | 0.72 |
▼Loop 740 - einspline_spo_ref.hpp:219-227 - exec– | 0.01 | 0 |
○Loop 741 - einspline_spo_ref.hpp:223-227 - exec | 0.73 | 0.71 |
○Loop 742 - einspline_spo_ref.hpp:206-207 - exec | 0 | 0 |