Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ... | Module: exec | Source: einspline_spo_ref.hpp:172-189 [...] | Coverage: 24.91% |
---|
Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ... | Module: exec | Source: einspline_spo_ref.hpp:172-189 [...] | Coverage: 24.91% |
---|
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 217 - 217 |
-------------------------------------------------------------------------------- |
217: inline const PosType& activeR(int iat) const { return (activePtcl == iat) ? activePos : R[iat]; } |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (unsigned d = 0; d < D; ++d) |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 191 - 191 |
-------------------------------------------------------------------------------- |
191: if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0) |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 47 - 49 |
-------------------------------------------------------------------------------- |
47: T sf = std::floor(x); |
48: T dx2 = x - sf; |
49: int ind2 = std::min(std::max(0, static_cast<int>(sf)), nmax); |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 43 - 74 |
-------------------------------------------------------------------------------- |
43: y -= spline_m->y_grid.start; |
44: z -= spline_m->z_grid.start; |
45: T tx, ty, tz; |
46: int ix, iy, iz; |
47: spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1); |
48: spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1); |
49: spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1); |
[...] |
56: const intptr_t xs = spline_m->x_stride; |
57: const intptr_t ys = spline_m->y_stride; |
58: const intptr_t zs = spline_m->z_stride; |
[...] |
65: for (size_t i = 0; i < 4; i++) |
66: for (size_t j = 0; j < 4; j++) |
67: { |
68: const T pre00 = a[i] * b[j]; |
69: const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs; |
70: #pragma omp simd aligned(coefs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_) |
71: for (size_t n = 0; n < num_splines; n++) |
72: vals[n] += pre00 * |
73: (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] + |
74: c[3] * coefs[n + 3 * zs]); |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 172 - 189 |
-------------------------------------------------------------------------------- |
172: ScopedTimer local_timer(timer); |
173: |
174: auto u = Lattice.toUnit_floor(P.activeR(iat)); |
175: for (int i = 0; i < nBlocks; ++i) |
176: MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock); |
177: } |
178: |
179: inline void evaluate(const ParticleSet& P, int iat, ValueVector_t& psi_v) |
180: { |
181: evaluate_v(P, iat); |
182: |
183: for (int i = 0; i < nBlocks; ++i) |
184: { |
185: // in real simulation, phase needs to be applied. Here just fake computation |
186: const int first = i * nBlocks; |
187: std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first); |
188: } |
189: } |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249 |
-------------------------------------------------------------------------------- |
242: ScopeGuard(TIMER& t) : timer(t) { timer.start(); } |
[...] |
249: ~ScopeGuard() { timer.stop(); } |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152 |
-------------------------------------------------------------------------------- |
150: return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6], |
151: lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7], |
152: lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]); |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57 |
-------------------------------------------------------------------------------- |
54: a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03; |
55: a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13; |
56: a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23; |
57: a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33; |
/usr/lib64/gcc/x86_64-pc-linux-gnu/13.1.1/../../../../include/c++/13.1.1/bits/stl_algo.h: 731 - 757 |
-------------------------------------------------------------------------------- |
731: { return std::copy(__first, __first + __n, __result); } |
[...] |
757: if (__n2 <= 0) |
/usr/lib64/gcc/x86_64-pc-linux-gnu/13.1.1/../../../../include/c++/13.1.1/bits/stl_algobase.h: 238 - 931 |
-------------------------------------------------------------------------------- |
238: if (__b < __a) |
[...] |
398: { *__to = *__from; } |
[...] |
435: const ptrdiff_t _Num = __last - __first; |
436: if (__builtin_expect(_Num > 1, true)) |
437: __builtin_memmove(__result, __first, sizeof(_Tp) * _Num); |
[...] |
930: for (; __first != __last; ++__first) |
931: *__first = __tmp; |
/usr/lib64/gcc/x86_64-pc-linux-gnu/13.1.1/../../../../include/c++/13.1.1/bits/stl_vector.h: 1126 - 1258 |
-------------------------------------------------------------------------------- |
1126: return *(this->_M_impl._M_start + __n); |
[...] |
1258: { return _M_data_ptr(this->_M_impl._M_start); } |
0x43ba20 PUSH %RBP |
0x43ba21 MOV %RSP,%RBP |
0x43ba24 PUSH %R15 |
0x43ba26 PUSH %R14 |
0x43ba28 PUSH %R13 |
0x43ba2a PUSH %R12 |
0x43ba2c PUSH %RBX |
0x43ba2d AND $-0x20,%RSP |
0x43ba31 SUB $0x1e0,%RSP |
0x43ba38 MOV %RCX,0x88(%RSP) |
0x43ba40 MOV %EDX,%R12D |
0x43ba43 MOV %RSI,%R14 |
0x43ba46 MOV %RDI,%RBX |
0x43ba49 MOV 0x348(%RDI),%RDI |
0x43ba50 MOV %RDI,0x90(%RSP) |
0x43ba58 CALL 464ec0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv> |
0x43ba5d MOVSXD %R12D,%RAX |
0x43ba60 LEA (%RAX,%RAX,2),%RCX |
0x43ba64 SAL $0x3,%RCX |
0x43ba68 ADD 0x5e8(%R14),%RCX |
0x43ba6f LEA 0x988(%R14),%RDX |
0x43ba76 CMP %EAX,0x984(%R14) |
0x43ba7d CMOVNE %RCX,%RDX |
0x43ba81 VMOVDDUP (%RDX),%XMM1 |
0x43ba85 VMULPD 0xd0(%RBX),%XMM1,%XMM0 |
0x43ba8d VMOVDDUP 0x8(%RDX),%XMM2 |
0x43ba92 VFMADD231PD 0xe8(%RBX),%XMM2,%XMM0 |
0x43ba9b VMOVDDUP 0x10(%RDX),%XMM3 |
0x43baa0 VFMADD231PD 0x100(%RBX),%XMM3,%XMM0 |
0x43baa9 VXORPD %XMM4,%XMM4,%XMM4 |
0x43baad VCMPPD $0x1,%XMM4,%XMM0,%K1 |
0x43bab4 VCMPPD $0xe,0x5d3b9(%RIP){1to0},%XMM0,%K0{%K1} |
0x43babf MOV %RBX,0x18(%RSP) |
0x43bac4 CMPL $0,0x30(%RBX) |
0x43bac8 JLE 43c1b4 |
0x43bace MOV 0x18(%RSP),%RAX |
0x43bad3 VMULSD 0xe0(%RAX),%XMM1,%XMM1 |
0x43badb VFMADD231SD 0xf8(%RAX),%XMM2,%XMM1 |
0x43bae4 VFMADD231SD 0x110(%RAX),%XMM3,%XMM1 |
0x43baed VROUNDPD $0x9,%XMM0,%XMM2 |
0x43baf3 KNOTW %K0,%K1 |
0x43baf7 VROUNDSD $0x9,%XMM1,%XMM1,%XMM3 |
0x43bafd VSUBPD %XMM2,%XMM0,%XMM0{%K1}{z} |
0x43bb03 VMOVUPD %XMM0,0x170(%RSP) |
0x43bb0c VSUBSD %XMM3,%XMM1,%XMM3 |
0x43bb10 VXORPD %XMM0,%XMM0,%XMM0 |
0x43bb14 VCMPSD $0x1,%XMM0,%XMM1,%K1 |
0x43bb1b VMOVAPD %XMM3,%XMM2 |
0x43bb1f VCMPSD $0xe,0x5d34e(%RIP),%XMM1,%K2 |
0x43bb2a VMOVSD %XMM0,%XMM2,%XMM2{%K1} |
0x43bb30 VMOVSD %XMM2,%XMM3,%XMM3{%K2} |
0x43bb36 VMOVUPD %XMM3,0x160(%RSP) |
0x43bb3f MOV 0x2e8(%RAX),%RCX |
0x43bb46 MOV %RCX,0xb0(%RSP) |
0x43bb4e MOV 0x300(%RAX),%RCX |
0x43bb55 MOV %RCX,0xa8(%RSP) |
0x43bb5d MOVSXD 0x40(%RAX),%RCX |
0x43bb61 LEA (,%RCX,8),%RDX |
0x43bb69 MOV %RDX,0x98(%RSP) |
0x43bb71 CMP $0x2,%RCX |
0x43bb75 MOV $0x1,%EDX |
0x43bb7a MOV %RCX,0x20(%RSP) |
0x43bb7f CMOVAE %RCX,%RDX |
0x43bb83 MOV %RDX,0x28(%RSP) |
0x43bb88 MOV %RDX,%RBX |
0x43bb8b AND $-0x8,%RBX |
0x43bb8f LEA -0x1(%RBX),%RCX |
0x43bb93 MOV %RCX,0x110(%RSP) |
0x43bb9b MOVSXD 0x30(%RAX),%RAX |
0x43bb9f MOV %RAX,0xa0(%RSP) |
0x43bba7 VMOVSD 0x5d2d1(%RIP),%XMM12 |
0x43bbaf XOR %EDX,%EDX |
0x43bbb1 VMOVDDUP 0x5a457(%RIP),%XMM0 |
0x43bbb9 VMOVUPD %XMM0,0x150(%RSP) |
0x43bbc2 JMP 43bbe9 |
0x43bbc4 NOPW %CS:(%RAX,%RAX,1) |
(827) 0x43bbd0 MOV 0xb8(%RSP),%RDX |
(827) 0x43bbd8 INC %RDX |
(827) 0x43bbdb CMP 0xa0(%RSP),%RDX |
(827) 0x43bbe3 JGE 43c1b4 |
(827) 0x43bbe9 MOV 0xb0(%RSP),%RAX |
(827) 0x43bbf1 MOV (%RAX,%RDX,8),%R14 |
(827) 0x43bbf5 VMOVUPD 0x160(%RSP),%XMM0 |
(827) 0x43bbfe VSUBSD 0x78(%R14),%XMM0,%XMM0 |
(827) 0x43bc04 VMULSD 0x98(%R14),%XMM0,%XMM0 |
(827) 0x43bc0d MOV 0x88(%R14),%R15D |
(827) 0x43bc14 DEC %R15D |
(827) 0x43bc17 VROUNDSD $0x9,%XMM0,%XMM0,%XMM1 |
(827) 0x43bc1d VCVTTSD2SI %XMM1,%EAX |
(827) 0x43bc21 MOV %EAX,%ECX |
(827) 0x43bc23 SAR $0x1f,%ECX |
(827) 0x43bc26 ANDN %EAX,%ECX,%EAX |
(827) 0x43bc2b CMP %EAX,%R15D |
(827) 0x43bc2e CMOVGE %EAX,%R15D |
(827) 0x43bc32 MOV %RDX,0xb8(%RSP) |
(827) 0x43bc3a LEA (%RDX,%RDX,2),%RAX |
(827) 0x43bc3e MOV 0xa8(%RSP),%RCX |
(827) 0x43bc46 MOV (%RCX,%RAX,8),%R12 |
(827) 0x43bc4a VSUBSD %XMM1,%XMM0,%XMM13 |
(827) 0x43bc4e VMULSD %XMM12,%XMM13,%XMM11 |
(827) 0x43bc53 VMOVSD 0x5a3b5(%RIP),%XMM8 |
(827) 0x43bc5b VSUBSD %XMM11,%XMM8,%XMM16 |
(827) 0x43bc61 VFMADD213SD 0x5a40d(%RIP),%XMM13,%XMM16 |
(827) 0x43bc6b VMULSD %XMM8,%XMM13,%XMM0 |
(827) 0x43bc70 VMULSD %XMM13,%XMM13,%XMM15 |
(827) 0x43bc75 VSUBSD %XMM0,%XMM8,%XMM1 |
(827) 0x43bc79 VMULSD %XMM1,%XMM13,%XMM1 |
(827) 0x43bc7d VUNPCKLPD %XMM1,%XMM0,%XMM0 |
(827) 0x43bc81 VADDPD 0x5d3b7(%RIP),%XMM0,%XMM0 |
(827) 0x43bc89 VUNPCKLPD %XMM13,%XMM15,%XMM14 |
(827) 0x43bc8e VFMADD213PD 0x5d3b9(%RIP),%XMM0,%XMM14 |
(827) 0x43bc97 VMOVSD 0x28(%R14),%XMM0 |
(827) 0x43bc9d VMOVSD 0x48(%R14),%XMM1 |
(827) 0x43bca3 VMOVHPD 0x50(%R14),%XMM0,%XMM0 |
(827) 0x43bca9 VMOVHPD 0x70(%R14),%XMM1,%XMM1 |
(827) 0x43bcaf VMOVUPD 0x170(%RSP),%XMM2 |
(827) 0x43bcb8 VSUBPD %XMM0,%XMM2,%XMM0 |
(827) 0x43bcbc VMULPD %XMM0,%XMM1,%XMM0 |
(827) 0x43bcc0 VRNDSCALEPD $0x9,%XMM0,%XMM17 |
(827) 0x43bcc7 VMOVD 0x38(%R14),%XMM1 |
(827) 0x43bccd VSUBPD %XMM17,%XMM0,%XMM0 |
(827) 0x43bcd3 VPINSRD $0x1,0x60(%R14),%XMM1,%XMM18 |
(827) 0x43bcdb VPERMILPD $0x1,%XMM0,%XMM1 |
(827) 0x43bce1 VMULSD %XMM0,%XMM12,%XMM2 |
(827) 0x43bce5 VSUBSD %XMM2,%XMM8,%XMM3 |
(827) 0x43bce9 VMULPD %XMM0,%XMM0,%XMM4 |
(827) 0x43bced VMOVDDUP %XMM0,%XMM5 |
(827) 0x43bcf1 VMOVUPD 0x150(%RSP),%XMM10 |
(827) 0x43bcfa VBLENDPD $0x1,%XMM3,%XMM10,%XMM3 |
(827) 0x43bd00 VMULPD %XMM3,%XMM5,%XMM3 |
(827) 0x43bd04 VMOVUPD 0x5d354(%RIP),%XMM9 |
(827) 0x43bd0c VADDPD %XMM3,%XMM9,%XMM5 |
(827) 0x43bd10 VUNPCKLPD %XMM4,%XMM0,%XMM6 |
(827) 0x43bd14 VMOVUPD 0x5d354(%RIP),%XMM7 |
(827) 0x43bd1c VFMADD213PD %XMM7,%XMM5,%XMM6 |
(827) 0x43bd21 VMOVUPD %XMM6,0x1a0(%RSP) |
(827) 0x43bd2a VPERMILPD $0x1,%XMM3,%XMM3 |
(827) 0x43bd30 VSUBSD %XMM3,%XMM8,%XMM3 |
(827) 0x43bd34 VFMADD213SD %XMM8,%XMM0,%XMM3 |
(827) 0x43bd39 VFMADD213SD %XMM12,%XMM0,%XMM3 |
(827) 0x43bd3e VMOVSD %XMM3,0x1b0(%RSP) |
(827) 0x43bd47 VMULSD %XMM4,%XMM2,%XMM2 |
(827) 0x43bd4b VMOVSD %XMM2,0x1b8(%RSP) |
(827) 0x43bd54 VMULSD %XMM1,%XMM12,%XMM2 |
(827) 0x43bd58 VSUBSD %XMM2,%XMM8,%XMM3 |
(827) 0x43bd5c VMULSD %XMM1,%XMM1,%XMM4 |
(827) 0x43bd60 VPERMILPD $0x3,%XMM0,%XMM5 |
(827) 0x43bd66 VBLENDPD $0x1,%XMM3,%XMM10,%XMM3 |
(827) 0x43bd6c VMULPD %XMM3,%XMM5,%XMM3 |
(827) 0x43bd70 VADDPD %XMM3,%XMM9,%XMM5 |
(827) 0x43bd74 VSHUFPD $0x1,%XMM4,%XMM0,%XMM0 |
(827) 0x43bd79 VFMADD213PD %XMM7,%XMM5,%XMM0 |
(827) 0x43bd7e VMOVUPD %XMM0,0x180(%RSP) |
(827) 0x43bd87 VPERMILPD $0x1,%XMM3,%XMM0 |
(827) 0x43bd8d VSUBSD %XMM0,%XMM8,%XMM0 |
(827) 0x43bd91 VFMADD213SD %XMM8,%XMM1,%XMM0 |
(827) 0x43bd96 VFMADD213SD %XMM12,%XMM1,%XMM0 |
(827) 0x43bd9b VMOVSD %XMM0,0x190(%RSP) |
(827) 0x43bda4 VMULSD %XMM4,%XMM2,%XMM0 |
(827) 0x43bda8 VMOVSD %XMM0,0x198(%RSP) |
(827) 0x43bdb1 VMOVDQU 0x10(%R14),%XMM2 |
(827) 0x43bdb7 MOV 0x20(%R14),%R13 |
(827) 0x43bdbb CMPL $0,0x20(%RSP) |
(827) 0x43bdc0 JE 43be55 |
(827) 0x43bdc6 MOV %R12,%RDI |
(827) 0x43bdc9 XOR %ESI,%ESI |
(827) 0x43bdcb MOV 0x98(%RSP),%RDX |
(827) 0x43bdd3 VMOVUPD %XMM13,0x70(%RSP) |
(827) 0x43bdd9 VMOVUPD %YMM14,0x120(%RSP) |
(827) 0x43bde2 VMOVSD %XMM11,0x8(%RSP) |
(827) 0x43bde8 VMOVUPD %XMM15,0x30(%RSP) |
(827) 0x43bdee VMOVSD %XMM16,0x10(%RSP) |
(827) 0x43bdf6 VMOVUPD %XMM17,0x60(%RSP) |
(827) 0x43bdfe VMOVDQU64 %XMM18,0x50(%RSP) |
(827) 0x43be06 VMOVDQU %XMM2,0x40(%RSP) |
(827) 0x43be0c VZEROUPPER |
(827) 0x43be0f CALL 4879b0 <_intel_fast_memset> |
(827) 0x43be14 VMOVDQU 0x40(%RSP),%XMM2 |
(827) 0x43be1a VMOVDQU64 0x50(%RSP),%XMM18 |
(827) 0x43be22 VMOVUPD 0x60(%RSP),%XMM17 |
(827) 0x43be2a VMOVSD 0x10(%RSP),%XMM16 |
(827) 0x43be32 VMOVUPD 0x30(%RSP),%XMM15 |
(827) 0x43be38 VMOVSD 0x8(%RSP),%XMM11 |
(827) 0x43be3e VMOVUPD 0x120(%RSP),%YMM14 |
(827) 0x43be47 VMOVUPD 0x70(%RSP),%XMM13 |
(827) 0x43be4d VMOVSD 0x5d02b(%RIP),%XMM12 |
(827) 0x43be55 CMPL $0,0x20(%RSP) |
(827) 0x43be5a JE 43bbd0 |
(827) 0x43be60 VFMADD213SD %XMM12,%XMM16,%XMM13 |
(827) 0x43be66 VPCMPEQD %XMM0,%XMM0,%XMM0 |
(827) 0x43be6a VPADDD %XMM0,%XMM18,%XMM0 |
(827) 0x43be70 VCVTTPD2DQ %XMM17,%XMM1 |
(827) 0x43be76 VPMAXSD 0x5a981(%RIP),%XMM1,%XMM1 |
(827) 0x43be7f VPMINSD %XMM1,%XMM0,%XMM0 |
(827) 0x43be84 MOVSXD %R15D,%RDX |
(827) 0x43be87 MOV %R13,%R11 |
(827) 0x43be8a IMUL %RDX,%R11 |
(827) 0x43be8e VPMOVSXDQ %XMM0,%XMM0 |
(827) 0x43be93 VPMULLQ %XMM0,%XMM2,%XMM1 |
(827) 0x43be99 MOV 0x8(%R14),%R8 |
(827) 0x43be9d VMULSD %XMM15,%XMM11,%XMM11 |
(827) 0x43bea2 VPEXTRQ $0x1,%XMM1,%RCX |
(827) 0x43bea8 VMOVQ %XMM1,%RSI |
(827) 0x43bead ADD %RCX,%RSI |
(827) 0x43beb0 VMOVQ %XMM2,%RCX |
(827) 0x43beb5 VPEXTRQ $0x1,%XMM2,%RDI |
(827) 0x43bebb VBROADCASTSD %XMM13,%YMM1 |
(827) 0x43bec0 VBROADCASTSD %XMM14,%YMM2 |
(827) 0x43bec5 VPERMPD $0x55,%YMM14,%YMM3 |
(827) 0x43becb VBROADCASTSD %XMM11,%YMM4 |
(827) 0x43bed0 ADD %RSI,%R11 |
(827) 0x43bed3 LEA (%R8,%R11,8),%R14 |
(827) 0x43bed7 MOV %RCX,0xc8(%RSP) |
(827) 0x43bedf LEA (,%RCX,8),%RCX |
(827) 0x43bee7 MOV %RCX,0xc0(%RSP) |
(827) 0x43beef MOV %RDI,0x50(%RSP) |
(827) 0x43bef4 LEA (,%RDI,8),%RCX |
(827) 0x43befc MOV %RCX,0x40(%RSP) |
(827) 0x43bf01 LEA 0x3(%RDX),%RDI |
(827) 0x43bf05 IMUL %R13,%RDI |
(827) 0x43bf09 ADD %RSI,%RDI |
(827) 0x43bf0c LEA (%R8,%RDI,8),%RCX |
(827) 0x43bf10 LEA 0x2(%RDX),%RAX |
(827) 0x43bf14 IMUL %R13,%RAX |
(827) 0x43bf18 ADD %RSI,%RAX |
(827) 0x43bf1b INC %RDX |
(827) 0x43bf1e IMUL %R13,%RDX |
(827) 0x43bf22 LEA (%R8,%RAX,8),%R9 |
(827) 0x43bf26 ADD %RSI,%RDX |
(827) 0x43bf29 MOV %R8,0x118(%RSP) |
(827) 0x43bf31 LEA (%R8,%RDX,8),%R10 |
(827) 0x43bf35 XOR %R8D,%R8D |
(827) 0x43bf38 JMP 43bfb9 |
0x43bf3a NOPW (%RAX,%RAX,1) |
(829) 0x43bf40 LEA 0x1(%RSI),%R8 |
(829) 0x43bf44 MOV 0xf8(%RSP),%R14 |
(829) 0x43bf4c MOV 0xc0(%RSP),%RCX |
(829) 0x43bf54 ADD %RCX,%R14 |
(829) 0x43bf57 MOV 0xe8(%RSP),%R15 |
(829) 0x43bf5f ADD %RCX,%R15 |
(829) 0x43bf62 MOV 0xd8(%RSP),%R9 |
(829) 0x43bf6a ADD %RCX,%R9 |
(829) 0x43bf6d MOV 0xd0(%RSP),%R10 |
(829) 0x43bf75 ADD %RCX,%R10 |
(829) 0x43bf78 MOV 0x100(%RSP),%R11 |
(829) 0x43bf80 MOV 0xc8(%RSP),%RCX |
(829) 0x43bf88 ADD %RCX,%R11 |
(829) 0x43bf8b MOV 0xf0(%RSP),%RDI |
(829) 0x43bf93 ADD %RCX,%RDI |
(829) 0x43bf96 MOV 0xe0(%RSP),%RAX |
(829) 0x43bf9e ADD %RCX,%RAX |
(829) 0x43bfa1 MOV 0x108(%RSP),%RDX |
(829) 0x43bfa9 ADD %RCX,%RDX |
(829) 0x43bfac MOV %R15,%RCX |
(829) 0x43bfaf CMP $0x3,%RSI |
(829) 0x43bfb3 JE 43bbd0 |
(829) 0x43bfb9 MOV %R8,0x60(%RSP) |
(829) 0x43bfbe VMOVSD 0x1a0(%RSP,%R8,8),%XMM10 |
(829) 0x43bfc8 MOV %RDX,0x108(%RSP) |
(829) 0x43bfd0 MOV %RDX,0x120(%RSP) |
(829) 0x43bfd8 MOV %RAX,0xe0(%RSP) |
(829) 0x43bfe0 MOV %RAX,0x8(%RSP) |
(829) 0x43bfe5 MOV %RDI,0xf0(%RSP) |
(829) 0x43bfed MOV %RDI,0x30(%RSP) |
(829) 0x43bff2 MOV %R11,0x100(%RSP) |
(829) 0x43bffa MOV %R10,0xd0(%RSP) |
(829) 0x43c002 MOV %R9,0xd8(%RSP) |
(829) 0x43c00a MOV %RCX,0xe8(%RSP) |
(829) 0x43c012 MOV %RCX,%RAX |
(829) 0x43c015 MOV %R14,0xf8(%RSP) |
(829) 0x43c01d XOR %ECX,%ECX |
(829) 0x43c01f JMP 43c073 |
0x43c021 NOPW %CS:(%RAX,%RAX,1) |
(830) 0x43c030 MOV 0x70(%RSP),%RSI |
(830) 0x43c035 LEA 0x1(%RSI),%RCX |
(830) 0x43c039 MOV 0x40(%RSP),%RDX |
(830) 0x43c03e ADD %RDX,%R14 |
(830) 0x43c041 ADD %RDX,%RAX |
(830) 0x43c044 ADD %RDX,%R9 |
(830) 0x43c047 ADD %RDX,%R10 |
(830) 0x43c04a MOV 0x50(%RSP),%RDX |
(830) 0x43c04f ADD %RDX,%R11 |
(830) 0x43c052 ADD %RDX,0x30(%RSP) |
(830) 0x43c057 ADD %RDX,0x8(%RSP) |
(830) 0x43c05c ADD %RDX,0x120(%RSP) |
(830) 0x43c064 CMP $0x3,%RSI |
(830) 0x43c068 MOV 0x60(%RSP),%RSI |
(830) 0x43c06d JE 43bf40 |
(830) 0x43c073 VMULSD 0x180(%RSP,%RCX,8),%XMM10,%XMM6 |
(830) 0x43c07c TEST %RBX,%RBX |
(830) 0x43c07f MOV %RCX,0x70(%RSP) |
(830) 0x43c084 JE 43c110 |
(830) 0x43c08a VBROADCASTSD %XMM6,%YMM7 |
(830) 0x43c08f XOR %ECX,%ECX |
(830) 0x43c091 MOV 0x110(%RSP),%RDX |
(830) 0x43c099 NOPL (%RAX) |
(831) 0x43c0a0 VMULPD 0x20(%R14,%RCX,8),%YMM1,%YMM8 |
(831) 0x43c0a7 VMULPD (%R14,%RCX,8),%YMM1,%YMM9 |
(831) 0x43c0ad VFMADD231PD (%R10,%RCX,8),%YMM2,%YMM9 |
(831) 0x43c0b3 VFMADD231PD 0x20(%R10,%RCX,8),%YMM2,%YMM8 |
(831) 0x43c0ba VFMADD231PD 0x20(%R9,%RCX,8),%YMM3,%YMM8 |
(831) 0x43c0c1 VFMADD231PD (%R9,%RCX,8),%YMM3,%YMM9 |
(831) 0x43c0c7 VFMADD231PD (%RAX,%RCX,8),%YMM4,%YMM9 |
(831) 0x43c0cd VFMADD231PD 0x20(%RAX,%RCX,8),%YMM4,%YMM8 |
(831) 0x43c0d4 VFMADD213PD 0x20(%R12,%RCX,8),%YMM7,%YMM8 |
(831) 0x43c0db VFMADD213PD (%R12,%RCX,8),%YMM7,%YMM9 |
(831) 0x43c0e1 VMOVUPD %YMM9,(%R12,%RCX,8) |
(831) 0x43c0e7 VMOVUPD %YMM8,0x20(%R12,%RCX,8) |
(831) 0x43c0ee ADD $0x8,%RCX |
(831) 0x43c0f2 CMP %RDX,%RCX |
(831) 0x43c0f5 JBE 43c0a0 |
(830) 0x43c0f7 MOV %RBX,%R15 |
(830) 0x43c0fa CMP %RBX,0x28(%RSP) |
(830) 0x43c0ff JE 43c030 |
(830) 0x43c105 JMP 43c113 |
0x43c107 NOPW (%RAX,%RAX,1) |
(830) 0x43c110 XOR %R15D,%R15D |
(830) 0x43c113 LEA (%R15,%R11,1),%RCX |
(830) 0x43c117 MOV %R11,0x10(%RSP) |
(830) 0x43c11c MOV 0x118(%RSP),%R11 |
(830) 0x43c124 LEA (%R11,%RCX,8),%RDX |
(830) 0x43c128 MOV 0x28(%RSP),%RDI |
(830) 0x43c12d SUB %R15,%RDI |
(830) 0x43c130 LEA (%R12,%R15,8),%RCX |
(830) 0x43c134 MOV 0x30(%RSP),%RSI |
(830) 0x43c139 ADD %R15,%RSI |
(830) 0x43c13c LEA (%R11,%RSI,8),%RSI |
(830) 0x43c140 MOV %RBX,%R13 |
(830) 0x43c143 MOV 0x8(%RSP),%RBX |
(830) 0x43c148 ADD %R15,%RBX |
(830) 0x43c14b LEA (%R11,%RBX,8),%R8 |
(830) 0x43c14f MOV %R13,%RBX |
(830) 0x43c152 ADD 0x120(%RSP),%R15 |
(830) 0x43c15a LEA (%R11,%R15,8),%R15 |
(830) 0x43c15e MOV 0x10(%RSP),%R11 |
(830) 0x43c163 XOR %R13D,%R13D |
(830) 0x43c166 NOPW %CS:(%RAX,%RAX,1) |
(828) 0x43c170 VMOVSD (%R15,%R13,8),%XMM7 |
(828) 0x43c176 VMOVHPD (%R8,%R13,8),%XMM7,%XMM7 |
(828) 0x43c17c VMULPD %XMM7,%XMM14,%XMM7 |
(828) 0x43c180 VPERMILPD $0x1,%XMM7,%XMM5 |
(828) 0x43c186 VMOVSD (%RDX,%R13,8),%XMM0 |
(828) 0x43c18c VFMADD132SD %XMM13,%XMM7,%XMM0 |
(828) 0x43c191 VFMADD231SD (%RSI,%R13,8),%XMM11,%XMM5 |
(828) 0x43c197 VADDSD %XMM0,%XMM5,%XMM0 |
(828) 0x43c19b VFMADD213SD (%RCX,%R13,8),%XMM6,%XMM0 |
(828) 0x43c1a1 VMOVSD %XMM0,(%RCX,%R13,8) |
(828) 0x43c1a7 INC %R13 |
(828) 0x43c1aa CMP %R13,%RDI |
(828) 0x43c1ad JNE 43c170 |
(830) 0x43c1af JMP 43c030 |
0x43c1b4 MOV 0x90(%RSP),%RDI |
0x43c1bc VZEROUPPER |
0x43c1bf CALL 4650a0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv> |
0x43c1c4 MOV 0x18(%RSP),%R12 |
0x43c1c9 MOV 0x30(%R12),%EAX |
0x43c1ce TEST %EAX,%EAX |
0x43c1d0 MOV 0x88(%RSP),%R15 |
0x43c1d8 JLE 43c252 |
0x43c1da XOR %EBX,%EBX |
0x43c1dc XOR %R14D,%R14D |
0x43c1df JMP 43c20c |
0x43c1e1 NOPW %CS:(%RAX,%RAX,1) |
(826) 0x43c1f0 MOV %ECX,%EDX |
(826) 0x43c1f2 SAL $0x3,%RDX |
(826) 0x43c1f6 CALL 404090 <memmove@plt> |
(826) 0x43c1fb MOV 0x30(%R12),%EAX |
(826) 0x43c200 MOVSXD %EAX,%RCX |
(826) 0x43c203 ADD $0x18,%RBX |
(826) 0x43c207 CMP %RCX,%R14 |
(826) 0x43c20a JGE 43c252 |
(826) 0x43c20c MOV %R14D,%EDX |
(826) 0x43c20f IMUL %EAX,%EDX |
(826) 0x43c212 INC %R14 |
(826) 0x43c215 MOV 0x40(%R12),%ECX |
(826) 0x43c21a IMUL %R14D,%ECX |
(826) 0x43c21e MOV 0x8(%R12),%ESI |
(826) 0x43c223 CMP %ECX,%ESI |
(826) 0x43c225 CMOVL %ESI,%ECX |
(826) 0x43c228 SUB %EDX,%ECX |
(826) 0x43c22a JLE 43c200 |
(826) 0x43c22c MOV 0x300(%R12),%RSI |
(826) 0x43c234 MOV (%RSI,%RBX,1),%RSI |
(826) 0x43c238 MOVSXD %EDX,%RDI |
(826) 0x43c23b SAL $0x3,%RDI |
(826) 0x43c23f ADD 0x18(%R15),%RDI |
(826) 0x43c243 CMP $0x1,%ECX |
(826) 0x43c246 JNE 43c1f0 |
(826) 0x43c248 VMOVSD (%RSI),%XMM0 |
(826) 0x43c24c VMOVSD %XMM0,(%RDI) |
(826) 0x43c250 JMP 43c200 |
0x43c252 LEA -0x28(%RBP),%RSP |
0x43c256 POP %RBX |
0x43c257 POP %R12 |
0x43c259 POP %R13 |
0x43c25b POP %R14 |
0x43c25d POP %R15 |
0x43c25f POP %RBP |
0x43c260 RET |
0x43c261 MOV %RAX,%RDI |
0x43c264 CALL 40d590 <__clang_call_terminate> |
0x43c269 NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:194 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:214 | exec |
○ | main.extracted.104 | refwrap.h:347 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | main | miniqmc.cpp:404 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | einspline_spo_ref.hpp:172-189 |
Module | exec |
nb instructions | 102 |
nb uops | 112 |
loop length | 552 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 14 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 28.00 cycles |
front end | 28.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 11.25 | 11.25 | 18.33 | 18.33 | 22.00 | 11.25 | 11.25 | 18.33 |
cycles | 11.25 | 11.25 | 18.33 | 18.33 | 22.00 | 11.25 | 11.25 | 18.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 26.96 |
Stall cycles | 0.00 |
Front-end | 28.00 |
Dispatch | 22.00 |
Overall L1 | 28.00 |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 48% |
load | 30% |
store | 100% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 54% |
all | 33% |
load | 25% |
store | 23% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 46% |
all | 12% |
load | 8% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 16% |
store | 25% |
mul | 18% |
add-sub | 18% |
fma | 18% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 19% |
all | 16% |
load | 14% |
store | 15% |
mul | 18% |
add-sub | 18% |
fma | 18% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 17% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
AND $-0x20,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SUB $0x1e0,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x348(%RDI),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RDI,0x90(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 464ec0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOVSXD %R12D,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RAX,2),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
ADD 0x5e8(%R14),%RCX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
LEA 0x988(%R14),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,0x984(%R14) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
CMOVNE %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
VMOVDDUP (%RDX),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD 0xd0(%RBX),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVDDUP 0x8(%RDX),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD 0xe8(%RBX),%XMM2,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVDDUP 0x10(%RDX),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD 0x100(%RBX),%XMM3,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCMPPD $0x1,%XMM4,%XMM0,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VCMPPD $0xe,0x5d3b9(%RIP){1to0},%XMM0,%K0{%K1} | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV %RBX,0x18(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMPL $0,0x30(%RBX) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JLE 43c1b4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x18(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0xe0(%RAX),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0xf8(%RAX),%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x110(%RAX),%XMM3,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x9,%XMM0,%XMM2 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
KNOTW %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VROUNDSD $0x9,%XMM1,%XMM1,%XMM3 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBPD %XMM2,%XMM0,%XMM0{%K1}{z} | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %XMM0,0x170(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VSUBSD %XMM3,%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCMPSD $0x1,%XMM0,%XMM1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVAPD %XMM3,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCMPSD $0xe,0x5d34e(%RIP),%XMM1,%K2 | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVSD %XMM0,%XMM2,%XMM2{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM2,%XMM3,%XMM3{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVUPD %XMM3,0x160(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x2e8(%RAX),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RCX,0xb0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x300(%RAX),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RCX,0xa8(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVSXD 0x40(%RAX),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP $0x2,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV $0x1,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMOVAE %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RBX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x110(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVSXD 0x30(%RAX),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RAX,0xa0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x5d2d1(%RIP),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDDUP 0x5a457(%RIP),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %XMM0,0x150(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 43bbe9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x90(%RSP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4650a0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV 0x18(%RSP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x30(%R12),%EAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x88(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JLE 43c252 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 43c20c | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 40d590 <__clang_call_terminate> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | einspline_spo_ref.hpp:172-189 |
Module | exec |
nb instructions | 102 |
nb uops | 112 |
loop length | 552 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 14 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 28.00 cycles |
front end | 28.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 11.25 | 11.25 | 18.33 | 18.33 | 22.00 | 11.25 | 11.25 | 18.33 |
cycles | 11.25 | 11.25 | 18.33 | 18.33 | 22.00 | 11.25 | 11.25 | 18.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 26.96 |
Stall cycles | 0.00 |
Front-end | 28.00 |
Dispatch | 22.00 |
Overall L1 | 28.00 |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 48% |
load | 30% |
store | 100% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 54% |
all | 33% |
load | 25% |
store | 23% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 46% |
all | 12% |
load | 8% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | 16% |
store | 25% |
mul | 18% |
add-sub | 18% |
fma | 18% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 19% |
all | 16% |
load | 14% |
store | 15% |
mul | 18% |
add-sub | 18% |
fma | 18% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 17% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
AND $-0x20,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SUB $0x1e0,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x348(%RDI),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RDI,0x90(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 464ec0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE5startEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOVSXD %R12D,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RAX,2),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
ADD 0x5e8(%R14),%RCX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
LEA 0x988(%R14),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,0x984(%R14) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
CMOVNE %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
VMOVDDUP (%RDX),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD 0xd0(%RBX),%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVDDUP 0x8(%RDX),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD 0xe8(%RBX),%XMM2,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVDDUP 0x10(%RDX),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD 0x100(%RBX),%XMM3,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCMPPD $0x1,%XMM4,%XMM0,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VCMPPD $0xe,0x5d3b9(%RIP){1to0},%XMM0,%K0{%K1} | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV %RBX,0x18(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMPL $0,0x30(%RBX) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JLE 43c1b4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x18(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0xe0(%RAX),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0xf8(%RAX),%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD 0x110(%RAX),%XMM3,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x9,%XMM0,%XMM2 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
KNOTW %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VROUNDSD $0x9,%XMM1,%XMM1,%XMM3 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VSUBPD %XMM2,%XMM0,%XMM0{%K1}{z} | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %XMM0,0x170(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VSUBSD %XMM3,%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCMPSD $0x1,%XMM0,%XMM1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVAPD %XMM3,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VCMPSD $0xe,0x5d34e(%RIP),%XMM1,%K2 | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVSD %XMM0,%XMM2,%XMM2{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM2,%XMM3,%XMM3{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVUPD %XMM3,0x160(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x2e8(%RAX),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RCX,0xb0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x300(%RAX),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RCX,0xa8(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVSXD 0x40(%RAX),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP $0x2,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV $0x1,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMOVAE %RCX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
AND $-0x8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x1(%RBX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x110(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOVSXD 0x30(%RAX),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RAX,0xa0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD 0x5d2d1(%RIP),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVDDUP 0x5a457(%RIP),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %XMM0,0x150(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 43bbe9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x90(%RSP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4650a0 <_ZN11qmcplusplus9TimerTypeINS_8CPUClockEE4stopEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV 0x18(%RSP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x30(%R12),%EAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x88(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JLE 43c252 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 43c20c | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 40d590 <__clang_call_terminate> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼miniqmcreference::einspline_spo_ref | 24.91 | 16.67 |
▼Loop 827 - MultiBsplineRef.hpp:43-74 - exec– | 0.02 | 0.01 |
▼Loop 829 - MultiBsplineRef.hpp:65-73 - exec– | 0.01 | 0 |
▼Loop 830 - MultiBsplineRef.hpp:66-73 - exec– | 0.01 | 0 |
○Loop 831 - MultiBsplineRef.hpp:70-73 - exec | 24.84 | 16.62 |
○Loop 828 - MultiBsplineRef.hpp:70-73 - exec | 0 | 0 |
○Loop 826 - stl_algobase.h:238-437 - exec | 0 | 0 |