Loop Id: 838 | Module: exec | Source: MultiBsplineRef.hpp:234-270 [...] | Coverage: 0.02% |
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Loop Id: 838 | Module: exec | Source: MultiBsplineRef.hpp:234-270 [...] | Coverage: 0.02% |
---|
0x43cbb0 MOV 0x10(%RSP),%RCX |
0x43cbb5 LEA 0x1(%RCX),%RAX |
0x43cbb9 CMP $0x3,%RCX |
0x43cbbd MOV %RAX,0x10(%RSP) |
0x43cbc2 MOV 0x20(%RSP),%RDX |
0x43cbc7 JE 43cb40 |
0x43cbcd TEST %EDX,%EDX |
0x43cbcf JLE 43cbb0 |
0x43cbd1 MOV 0x10(%RSP),%RCX |
0x43cbd6 VMOVSD 0x2e0(%RSP,%RCX,8),%XMM0 |
0x43cbdf VMULSD 0x48(%RSP),%XMM0,%XMM21 |
0x43cbe7 VMOVSD 0x158(%RSP),%XMM1 |
0x43cbf0 VMULSD %XMM1,%XMM0,%XMM28 |
0x43cbf6 VMOVSD 0x150(%RSP),%XMM2 |
0x43cbff VMULSD %XMM2,%XMM0,%XMM30 |
0x43cc05 VMOVSD 0x1c0(%RSP,%RCX,8),%XMM0 |
0x43cc0e VMULSD %XMM1,%XMM0,%XMM1 |
0x43cc12 VMULSD %XMM2,%XMM0,%XMM3 |
0x43cc16 VMULSD 0x180(%RSP,%RCX,8),%XMM2,%XMM2 |
0x43cc1f MOV 0x140(%RSP),%RAX |
0x43cc27 IMUL %RCX,%RAX |
0x43cc2b ADD 0x148(%RSP),%RAX |
0x43cc33 VMOVQ %RAX,%XMM0 |
0x43cc38 VPADDQ 0x400(%RSP),%XMM0,%XMM0 |
0x43cc41 VPBROADCASTQ %XMM0,%YMM0 |
0x43cc46 VPADDQ 0x3e0(%RSP),%YMM0,%YMM0 |
0x43cc4f VPEXTRQ $0x1,%XMM0,%RDX |
0x43cc55 VMOVQ %XMM0,%RCX |
0x43cc5a VEXTRACTI128 $0x1,%YMM0,%XMM0 |
0x43cc60 VMOVQ %XMM0,%RSI |
0x43cc65 VPEXTRQ $0x1,%XMM0,%RBX |
0x43cc6b MOV 0x138(%RSP),%R12 |
0x43cc73 TEST %R12,%R12 |
0x43cc76 JE 43d070 |
0x43cc7c VMOVAPD %XMM21,%XMM0 |
0x43cc82 VMOVAPD %YMM20,%YMM21 |
0x43cc88 VMOVAPD %YMM19,%YMM20 |
0x43cc8e VMOVUPD 0x340(%RSP),%YMM19 |
0x43cc96 VMOVUPD 0x360(%RSP),%YMM18 |
0x43cc9e VMOVUPD 0x380(%RSP),%YMM17 |
0x43cca6 VMOVUPD %XMM0,0xa0(%RSP) |
0x43ccaf VBROADCASTSD %XMM0,%YMM31 |
0x43ccb5 VMOVUPD %XMM1,0xe0(%RSP) |
0x43ccbe VBROADCASTSD %XMM1,%YMM8 |
0x43ccc3 VMOVUPD %XMM28,0x90(%RSP) |
0x43cccb VBROADCASTSD %XMM28,%YMM9 |
0x43ccd1 VMOVUPD %XMM2,0xc0(%RSP) |
0x43ccda VBROADCASTSD %XMM2,%YMM22 |
0x43cce0 VMOVUPD %XMM3,0xd0(%RSP) |
0x43cce9 VBROADCASTSD %XMM3,%YMM23 |
0x43ccef VMOVUPD %XMM30,0x80(%RSP) |
0x43ccf7 VBROADCASTSD %XMM30,%YMM24 |
0x43ccfd MOV 0x70(%RSP),%RAX |
0x43cd02 MOV %RBX,0x50(%RSP) |
0x43cd07 LEA (%RAX,%RBX,8),%R8 |
0x43cd0b MOV %RSI,0x58(%RSP) |
0x43cd10 LEA (%RAX,%RSI,8),%R10 |
0x43cd14 MOV %RDX,0x60(%RSP) |
0x43cd19 LEA (%RAX,%RDX,8),%R9 |
0x43cd1d MOV %RCX,0x68(%RSP) |
0x43cd22 LEA (%RAX,%RCX,8),%R11 |
0x43cd26 XOR %R13D,%R13D |
0x43cd29 MOV 0x18(%RSP),%R15 |
0x43cd2e MOV 0x28(%RSP),%RSI |
0x43cd33 MOV 0x30(%RSP),%RDX |
0x43cd38 MOV 0x8(%RSP),%RBX |
0x43cd3d MOV 0x40(%RSP),%RCX |
0x43cd42 VMOVUPD 0x3c0(%RSP),%YMM2 |
0x43cd4b VMOVUPD 0x3a0(%RSP),%YMM1 |
0x43cd54 NOPW %CS:(%RAX,%RAX,1) |
(840) 0x43cd60 VMOVUPD (%R11,%R13,8),%YMM28 |
(840) 0x43cd67 VMOVUPD 0x20(%R11,%R13,8),%YMM27 |
(840) 0x43cd6f VMOVUPD (%R9,%R13,8),%YMM30 |
(840) 0x43cd76 VMOVUPD 0x20(%R9,%R13,8),%YMM7 |
(840) 0x43cd7d VMOVUPD (%R10,%R13,8),%YMM6 |
(840) 0x43cd83 VMOVUPD 0x20(%R10,%R13,8),%YMM0 |
(840) 0x43cd8a VMOVUPD (%R8,%R13,8),%YMM5 |
(840) 0x43cd90 VMOVUPD 0x20(%R8,%R13,8),%YMM11 |
(840) 0x43cd97 VMULPD %YMM29,%YMM27,%YMM25 |
(840) 0x43cd9d VMULPD %YMM29,%YMM28,%YMM26 |
(840) 0x43cda3 VMULPD %YMM13,%YMM11,%YMM10 |
(840) 0x43cda8 VMULPD %YMM5,%YMM13,%YMM4 |
(840) 0x43cdac VFMADD231PD %YMM2,%YMM30,%YMM26 |
(840) 0x43cdb2 VFMADD231PD %YMM2,%YMM7,%YMM25 |
(840) 0x43cdb8 VFMADD231PD %YMM1,%YMM0,%YMM25 |
(840) 0x43cdbe VFMADD231PD %YMM1,%YMM6,%YMM26 |
(840) 0x43cdc4 VFMADD231PD %YMM4,%YMM17,%YMM26 |
(840) 0x43cdca VFMADD231PD %YMM10,%YMM17,%YMM25 |
(840) 0x43cdd0 VMOVAPD %YMM29,%YMM3 |
(840) 0x43cdd6 VMULPD %YMM18,%YMM28,%YMM29 |
(840) 0x43cddc VMULPD %YMM19,%YMM7,%YMM12 |
(840) 0x43cde2 VFMADD231PD %YMM11,%YMM21,%YMM12 |
(840) 0x43cde8 VMULPD %YMM19,%YMM30,%YMM11 |
(840) 0x43cdee VFMADD231PD %YMM5,%YMM21,%YMM11 |
(840) 0x43cdf4 VFMADD231PD %YMM20,%YMM6,%YMM29 |
(840) 0x43cdfa VFMADD231PD %YMM11,%YMM13,%YMM29 |
(840) 0x43ce00 VMOVUPD (%RSI,%R13,8),%YMM11 |
(840) 0x43ce06 VMULPD %YMM18,%YMM27,%YMM5 |
(840) 0x43ce0c VFMADD231PD %YMM26,%YMM31,%YMM11 |
(840) 0x43ce12 VMOVUPD %YMM11,(%RSI,%R13,8) |
(840) 0x43ce18 VMOVUPD 0x20(%RSI,%R13,8),%YMM11 |
(840) 0x43ce1f LEA (%RSI,%R13,8),%RAX |
(840) 0x43ce23 VFMADD231PD %YMM25,%YMM31,%YMM11 |
(840) 0x43ce29 VMOVUPD %YMM11,0x20(%RSI,%R13,8) |
(840) 0x43ce30 VMOVUPD (%RAX,%R14,8),%YMM11 |
(840) 0x43ce36 VFMADD231PD %YMM20,%YMM0,%YMM5 |
(840) 0x43ce3c VFMADD231PD %YMM26,%YMM8,%YMM11 |
(840) 0x43ce42 VMOVUPD %YMM11,(%RAX,%R14,8) |
(840) 0x43ce48 VMOVUPD 0x20(%RAX,%R14,8),%YMM11 |
(840) 0x43ce4f VFMADD231PD %YMM25,%YMM8,%YMM11 |
(840) 0x43ce55 VMOVUPD %YMM11,0x20(%RAX,%R14,8) |
(840) 0x43ce5c LEA (%RAX,%R14,8),%RAX |
(840) 0x43ce60 VMOVUPD (%RDI,%RAX,1),%YMM11 |
(840) 0x43ce65 VFMADD231PD %YMM12,%YMM13,%YMM5 |
(840) 0x43ce6a VFMADD231PD %YMM9,%YMM29,%YMM11 |
(840) 0x43ce70 VMOVUPD %YMM11,(%RDI,%RAX,1) |
(840) 0x43ce75 VMOVUPD 0x20(%RDI,%RAX,1),%YMM11 |
(840) 0x43ce7b VFMADD231PD %YMM9,%YMM5,%YMM11 |
(840) 0x43ce80 VMOVUPD %YMM11,0x20(%RDI,%RAX,1) |
(840) 0x43ce86 LEA (%RAX,%RDI,1),%RAX |
(840) 0x43ce8a VMOVUPD (%RDI,%RAX,1),%YMM11 |
(840) 0x43ce8f VFMADD231PD %YMM26,%YMM22,%YMM11 |
(840) 0x43ce95 VMOVUPD %YMM11,(%RDI,%RAX,1) |
(840) 0x43ce9a VMOVUPD 0x20(%RDI,%RAX,1),%YMM11 |
(840) 0x43cea0 VFMADD231PD %YMM25,%YMM22,%YMM11 |
(840) 0x43cea6 VMOVUPD %YMM11,0x20(%RDI,%RAX,1) |
(840) 0x43ceac LEA (%RAX,%RDI,1),%RAX |
(840) 0x43ceb0 VMOVUPD (%RDI,%RAX,1),%YMM11 |
(840) 0x43ceb5 VFMADD231PD %YMM23,%YMM29,%YMM11 |
(840) 0x43cebb VMOVUPD %YMM11,(%RDI,%RAX,1) |
(840) 0x43cec0 VMOVUPD 0x20(%RDI,%RAX,1),%YMM11 |
(840) 0x43cec6 VFMADD231PD %YMM23,%YMM5,%YMM11 |
(840) 0x43cecc VMOVUPD %YMM11,0x20(%RDI,%RAX,1) |
(840) 0x43ced2 VFMADD213PD %YMM10,%YMM14,%YMM27 |
(840) 0x43ced8 VFMADD231PD %YMM7,%YMM15,%YMM27 |
(840) 0x43cede VFMADD231PD %YMM0,%YMM16,%YMM27 |
(840) 0x43cee4 VFMADD213PD %YMM4,%YMM14,%YMM28 |
(840) 0x43ceea VFMADD231PD %YMM30,%YMM15,%YMM28 |
(840) 0x43cef0 VFMADD231PD %YMM6,%YMM16,%YMM28 |
(840) 0x43cef6 LEA (%RAX,%RDI,1),%RAX |
(840) 0x43cefa VFMADD213PD (%RDI,%RAX,1),%YMM24,%YMM28 |
(840) 0x43cf01 VMOVUPD %YMM28,(%RDI,%RAX,1) |
(840) 0x43cf08 VFMADD213PD 0x20(%RDI,%RAX,1),%YMM24,%YMM27 |
(840) 0x43cf10 VMOVUPD %YMM27,0x20(%RDI,%RAX,1) |
(840) 0x43cf18 VMOVUPD (%R15,%R13,8),%YMM0 |
(840) 0x43cf1e VFMADD231PD %YMM9,%YMM26,%YMM0 |
(840) 0x43cf24 VMOVUPD %YMM0,(%R15,%R13,8) |
(840) 0x43cf2a VMOVUPD 0x20(%R15,%R13,8),%YMM0 |
(840) 0x43cf31 VFMADD231PD %YMM9,%YMM25,%YMM0 |
(840) 0x43cf37 VMOVUPD %YMM0,0x20(%R15,%R13,8) |
(840) 0x43cf3e VMOVUPD (%RCX,%R13,8),%YMM0 |
(840) 0x43cf44 VFMADD231PD %YMM23,%YMM26,%YMM0 |
(840) 0x43cf4a VMOVUPD %YMM0,(%RCX,%R13,8) |
(840) 0x43cf50 VMOVUPD 0x20(%RCX,%R13,8),%YMM0 |
(840) 0x43cf57 VFMADD231PD %YMM23,%YMM25,%YMM0 |
(840) 0x43cf5d VMOVUPD %YMM0,0x20(%RCX,%R13,8) |
(840) 0x43cf64 VFMADD213PD (%RBX,%R13,8),%YMM24,%YMM29 |
(840) 0x43cf6b VMOVUPD %YMM29,(%RBX,%R13,8) |
(840) 0x43cf72 VMOVAPD %YMM3,%YMM29 |
(840) 0x43cf78 VFMADD213PD 0x20(%RBX,%R13,8),%YMM24,%YMM5 |
(840) 0x43cf80 VMOVUPD %YMM5,0x20(%RBX,%R13,8) |
(840) 0x43cf87 VFMADD213PD (%RDX,%R13,8),%YMM24,%YMM26 |
(840) 0x43cf8e VMOVUPD %YMM26,(%RDX,%R13,8) |
(840) 0x43cf95 VFMADD213PD 0x20(%RDX,%R13,8),%YMM24,%YMM25 |
(840) 0x43cf9d VMOVUPD %YMM25,0x20(%RDX,%R13,8) |
(840) 0x43cfa5 ADD $0x8,%R13 |
(840) 0x43cfa9 CMP %R12,%R13 |
(840) 0x43cfac JL 43cd60 |
0x43cfb2 MOV %R12,%R8 |
0x43cfb5 CMP 0x20(%RSP),%R12 |
0x43cfba VMOVUPD 0x170(%RSP),%XMM8 |
0x43cfc3 VMOVUPD 0x160(%RSP),%XMM9 |
0x43cfcc VMOVUPD 0x320(%RSP),%YMM10 |
0x43cfd5 VMOVUPD 0x260(%RSP),%XMM11 |
0x43cfde VMOVUPD 0x270(%RSP),%XMM12 |
0x43cfe7 VMOVUPD 0x280(%RSP),%XMM22 |
0x43cfef VMOVUPD 0x2d0(%RSP),%XMM23 |
0x43cff7 VMOVUPD 0x2c0(%RSP),%XMM24 |
0x43cfff VMOVUPD 0x2b0(%RSP),%XMM25 |
0x43d007 VMOVUPD 0x2a0(%RSP),%XMM26 |
0x43d00f VMOVUPD 0x290(%RSP),%XMM27 |
0x43d017 VMOVAPD %YMM20,%YMM19 |
0x43d01d VMOVAPD %YMM21,%YMM20 |
0x43d023 VMOVUPD 0xa0(%RSP),%XMM21 |
0x43d02b VMOVUPD 0x90(%RSP),%XMM28 |
0x43d033 VMOVUPD 0x80(%RSP),%XMM30 |
0x43d03b VMOVUPD 0xe0(%RSP),%XMM31 |
0x43d043 VMOVUPD 0xd0(%RSP),%XMM17 |
0x43d04b VMOVUPD 0xc0(%RSP),%XMM18 |
0x43d053 MOV 0x68(%RSP),%RCX |
0x43d058 MOV 0x60(%RSP),%RDX |
0x43d05d MOV 0x58(%RSP),%RSI |
0x43d062 MOV 0x50(%RSP),%RBX |
0x43d067 JE 43cbb0 |
0x43d06d JMP 43d085 |
0x43d070 XOR %R8D,%R8D |
0x43d073 VMOVAPD %XMM1,%XMM31 |
0x43d079 VMOVAPD %XMM3,%XMM17 |
0x43d07f VMOVAPD %XMM2,%XMM18 |
0x43d085 ADD %R8,%RBX |
0x43d088 MOV 0x70(%RSP),%RAX |
0x43d08d LEA (%RAX,%RBX,8),%R9 |
0x43d091 ADD %R8,%RSI |
0x43d094 LEA (%RAX,%RSI,8),%R10 |
0x43d098 ADD %R8,%RDX |
0x43d09b LEA (%RAX,%RDX,8),%R11 |
0x43d09f ADD %R8,%RCX |
0x43d0a2 LEA (%RAX,%RCX,8),%R13 |
0x43d0a6 MOV 0x20(%RSP),%RBX |
0x43d0ab SUB %R8,%RBX |
0x43d0ae MOV 0x30(%RSP),%RAX |
0x43d0b3 LEA (%RAX,%R8,8),%RSI |
0x43d0b7 MOV 0x18(%RSP),%R15 |
0x43d0bc LEA (%R15,%R8,8),%RCX |
0x43d0c0 MOV 0x8(%RSP),%RAX |
0x43d0c5 LEA (%RAX,%R8,8),%RAX |
0x43d0c9 LEA (%R14,%R8,1),%RDX |
0x43d0cd LEA (%R15,%RDX,8),%R12 |
0x43d0d1 MOV 0x28(%RSP),%RDX |
0x43d0d6 LEA (%RDX,%R8,8),%R15 |
0x43d0da XOR %R8D,%R8D |
0x43d0dd NOPL (%RAX) |
(839) 0x43d0e0 VMOVSD (%R13,%R8,8),%XMM0 |
(839) 0x43d0e7 VMOVSD (%R9,%R8,8),%XMM4 |
(839) 0x43d0ed VMOVSD (%R11,%R8,8),%XMM5 |
(839) 0x43d0f3 VMOVSD (%R10,%R8,8),%XMM6 |
(839) 0x43d0f9 VUNPCKLPD %XMM6,%XMM5,%XMM7 |
(839) 0x43d0fd VMULPD %XMM7,%XMM10,%XMM7 |
(839) 0x43d101 VMULSD %XMM4,%XMM8,%XMM1 |
(839) 0x43d105 VPERMILPD $0x1,%XMM7,%XMM3 |
(839) 0x43d10b VFMADD231SD %XMM0,%XMM11,%XMM7 |
(839) 0x43d110 VFMADD231SD %XMM27,%XMM1,%XMM3 |
(839) 0x43d116 VADDSD %XMM7,%XMM3,%XMM3 |
(839) 0x43d11a VMULSD %XMM0,%XMM12,%XMM7 |
(839) 0x43d11e VMULSD %XMM22,%XMM5,%XMM2 |
(839) 0x43d124 VFMADD231SD %XMM4,%XMM9,%XMM2 |
(839) 0x43d129 VFMADD231SD %XMM23,%XMM6,%XMM7 |
(839) 0x43d12f VFMADD231SD %XMM2,%XMM8,%XMM7 |
(839) 0x43d134 LEA (%R15,%R8,8),%RDX |
(839) 0x43d138 VMOVSD (%R15,%R8,8),%XMM2 |
(839) 0x43d13e VFMADD231SD %XMM3,%XMM21,%XMM2 |
(839) 0x43d144 VMOVSD %XMM2,(%R15,%R8,8) |
(839) 0x43d14a VMOVSD (%RDX,%R14,8),%XMM2 |
(839) 0x43d150 VFMADD231SD %XMM3,%XMM31,%XMM2 |
(839) 0x43d156 VMOVSD %XMM2,(%RDX,%R14,8) |
(839) 0x43d15c LEA (%RDX,%R14,8),%RDX |
(839) 0x43d160 VMOVSD (%RDI,%RDX,1),%XMM2 |
(839) 0x43d165 VFMADD231SD %XMM28,%XMM7,%XMM2 |
(839) 0x43d16b VMOVSD %XMM2,(%RDI,%RDX,1) |
(839) 0x43d170 LEA (%RDX,%RDI,1),%RDX |
(839) 0x43d174 VMOVSD (%RDI,%RDX,1),%XMM2 |
(839) 0x43d179 VFMADD231SD %XMM3,%XMM18,%XMM2 |
(839) 0x43d17f VMOVSD %XMM2,(%RDI,%RDX,1) |
(839) 0x43d184 LEA (%RDX,%RDI,1),%RDX |
(839) 0x43d188 VMOVSD (%RDI,%RDX,1),%XMM2 |
(839) 0x43d18d VFMADD231SD %XMM17,%XMM7,%XMM2 |
(839) 0x43d193 VMOVSD %XMM2,(%RDI,%RDX,1) |
(839) 0x43d198 LEA (%RDX,%RDI,1),%RDX |
(839) 0x43d19c VFMADD213SD %XMM1,%XMM24,%XMM0 |
(839) 0x43d1a2 VFMADD231SD %XMM5,%XMM25,%XMM0 |
(839) 0x43d1a8 VFMADD231SD %XMM6,%XMM26,%XMM0 |
(839) 0x43d1ae VFMADD213SD (%RDI,%RDX,1),%XMM30,%XMM0 |
(839) 0x43d1b5 VMOVSD %XMM0,(%RDI,%RDX,1) |
(839) 0x43d1ba VMOVSD (%RCX,%R8,8),%XMM0 |
(839) 0x43d1c0 VFMADD231SD %XMM28,%XMM3,%XMM0 |
(839) 0x43d1c6 VMOVSD %XMM0,(%RCX,%R8,8) |
(839) 0x43d1cc VMOVSD (%R12,%R8,8),%XMM0 |
(839) 0x43d1d2 VFMADD231SD %XMM17,%XMM3,%XMM0 |
(839) 0x43d1d8 VMOVSD %XMM0,(%R12,%R8,8) |
(839) 0x43d1de VFMADD213SD (%RAX,%R8,8),%XMM30,%XMM7 |
(839) 0x43d1e5 VMOVSD %XMM7,(%RAX,%R8,8) |
(839) 0x43d1eb VFMADD213SD (%RSI,%R8,8),%XMM30,%XMM3 |
(839) 0x43d1f2 VMOVSD %XMM3,(%RSI,%R8,8) |
(839) 0x43d1f8 INC %R8 |
(839) 0x43d1fb CMP %R8,%RBX |
(839) 0x43d1fe JNE 43d0e0 |
0x43d204 JMP 43cbb0 |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (unsigned d = 0; d < D; ++d) |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 234 - 270 |
-------------------------------------------------------------------------------- |
234: for (int j = 0; j < 4; j++) |
[...] |
241: const T pre20 = d2a[i] * b[j]; |
242: const T pre10 = da[i] * b[j]; |
243: const T pre00 = a[i] * b[j]; |
244: const T pre11 = da[i] * db[j]; |
245: const T pre01 = a[i] * db[j]; |
246: const T pre02 = a[i] * d2b[j]; |
247: |
248: const int iSplitPoint = num_splines; |
249: #pragma omp simd aligned(coefs, coefszs, coefs2zs, coefs3zs: QMC_SIMD_ALIGNMENT) simdlen(simdlen_) |
250: for (int n = 0; n < iSplitPoint; n++) |
251: { |
252: T coefsv = coefs[n]; |
253: T coefsvzs = coefszs[n]; |
254: T coefsv2zs = coefs2zs[n]; |
255: T coefsv3zs = coefs3zs[n]; |
256: |
257: T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs; |
258: T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs; |
259: T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs; |
260: |
261: hxx[n] += pre20 * sum0; |
262: hxy[n] += pre11 * sum0; |
263: hxz[n] += pre10 * sum1; |
264: hyy[n] += pre02 * sum0; |
265: hyz[n] += pre01 * sum1; |
266: hzz[n] += pre00 * sum2; |
267: gx[n] += pre10 * sum0; |
268: gy[n] += pre01 * sum0; |
269: gz[n] += pre00 * sum1; |
270: vals[n] += pre00 * sum0; |
/home/kcamus/qaas_runs/169-451-1869/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 71 - 71 |
-------------------------------------------------------------------------------- |
71: a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:100 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:202 | exec |
○ | main.extracted.104 | refwrap.h:347 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | main | miniqmc.cpp:404 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.67 |
CQA speedup if FP arith vectorized | 1.79 |
CQA speedup if fully vectorized | 6.37 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.20 |
Bottlenecks | |
Function | miniqmcreference::einspline_spo_ref |
Source | TinyVectorOps.h:59-59,MultiBsplineRef.hpp:234-270,MultiBsplineData.hpp:71-71 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 18.44 |
CQA cycles if no scalar integer | 11.06 |
CQA cycles if FP arith vectorized | 10.32 |
CQA cycles if fully vectorized | 2.89 |
Front-end cycles | 18.44 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 9.25 |
P1 cycles | 15.25 |
P2 cycles | 15.25 |
P3 cycles | 6.00 |
P4 cycles | 9.50 |
P5 cycles | 8.00 |
P6 cycles | 6.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 18.73 |
Stall cycles (UFS) | 0.06 |
Nb insns | 71.75 |
Nb uops | 73.00 |
Nb loads | 30.50 |
Nb stores | 6.00 |
Nb stack references | 25.25 |
FLOP/cycle | 0.24 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 4.50 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.72 |
Bytes prefetched | 0.00 |
Bytes loaded | 404.00 |
Bytes stored | 72.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 11.75 |
Stride indirect | 0.00 |
Vectorization ratio all | 31.64 |
Vectorization ratio load | 58.21 |
Vectorization ratio store | 27.27 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 20.74 |
Vector-efficiency ratio all | 18.53 |
Vector-efficiency ratio load | 24.41 |
Vector-efficiency ratio store | 15.91 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 16.87 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | micro-operation queue, |
Function | miniqmcreference::einspline_spo_ref |
Source | TinyVectorOps.h:59-59,MultiBsplineRef.hpp:234-270,MultiBsplineData.hpp:71-71 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 1.75 |
CQA cycles if no scalar integer | 1.75 |
CQA cycles if FP arith vectorized | 1.75 |
CQA cycles if fully vectorized | 0.22 |
Front-end cycles | 1.75 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 1.86 |
Stall cycles (UFS) | 0.00 |
Nb insns | 8.00 |
Nb uops | 7.00 |
Nb loads | 2.00 |
Nb stores | 1.00 |
Nb stack references | 2.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 13.71 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.10 |
CQA speedup if FP arith vectorized | 2.85 |
CQA speedup if fully vectorized | 10.78 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.55 |
Bottlenecks | micro-operation queue, |
Function | miniqmcreference::einspline_spo_ref |
Source | TinyVectorOps.h:59-59,MultiBsplineRef.hpp:234-270,MultiBsplineData.hpp:71-71 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.25 |
CQA cycles if no scalar integer | 7.75 |
CQA cycles if FP arith vectorized | 5.70 |
CQA cycles if fully vectorized | 1.51 |
Front-end cycles | 16.25 |
DIV/SQRT cycles | 10.50 |
P0 cycles | 10.50 |
P1 cycles | 10.00 |
P2 cycles | 10.00 |
P3 cycles | 1.00 |
P4 cycles | 10.50 |
P5 cycles | 10.50 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 16.56 |
Stall cycles (UFS) | 0.00 |
Nb insns | 62.00 |
Nb uops | 64.00 |
Nb loads | 20.00 |
Nb stores | 1.00 |
Nb stack references | 15.00 |
FLOP/cycle | 0.37 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 6.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.31 |
Bytes prefetched | 0.00 |
Bytes loaded | 192.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 12.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 22.22 |
Vectorization ratio load | 22.22 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 30.77 |
Vector-efficiency ratio all | 15.97 |
Vector-efficiency ratio load | 18.06 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.87 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.72 |
CQA speedup if FP arith vectorized | 1.79 |
CQA speedup if fully vectorized | 6.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.17 |
Bottlenecks | micro-operation queue, |
Function | miniqmcreference::einspline_spo_ref |
Source | TinyVectorOps.h:59-59,MultiBsplineRef.hpp:234-270,MultiBsplineData.hpp:71-71 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 31.00 |
CQA cycles if no scalar integer | 18.00 |
CQA cycles if FP arith vectorized | 17.31 |
CQA cycles if fully vectorized | 5.03 |
Front-end cycles | 31.00 |
DIV/SQRT cycles | 12.00 |
P0 cycles | 15.50 |
P1 cycles | 26.50 |
P2 cycles | 26.50 |
P3 cycles | 11.00 |
P4 cycles | 15.50 |
P5 cycles | 12.00 |
P6 cycles | 11.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 31.24 |
Stall cycles (UFS) | 0.00 |
Nb insns | 121.00 |
Nb uops | 123.00 |
Nb loads | 53.00 |
Nb stores | 11.00 |
Nb stack references | 42.00 |
FLOP/cycle | 0.19 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 6.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.87 |
Bytes prefetched | 0.00 |
Bytes loaded | 728.00 |
Bytes stored | 136.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 23.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 52.17 |
Vectorization ratio load | 75.00 |
Vectorization ratio store | 54.55 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.09 |
Vector-efficiency ratio all | 22.83 |
Vector-efficiency ratio load | 27.34 |
Vector-efficiency ratio store | 19.32 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 19.57 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.48 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 5.14 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | micro-operation queue, |
Function | miniqmcreference::einspline_spo_ref |
Source | TinyVectorOps.h:59-59,MultiBsplineRef.hpp:234-270,MultiBsplineData.hpp:71-71 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 24.75 |
CQA cycles if no scalar integer | 16.75 |
CQA cycles if FP arith vectorized | 16.50 |
CQA cycles if fully vectorized | 4.81 |
Front-end cycles | 24.75 |
DIV/SQRT cycles | 8.50 |
P0 cycles | 10.00 |
P1 cycles | 23.50 |
P2 cycles | 23.50 |
P3 cycles | 11.00 |
P4 cycles | 11.00 |
P5 cycles | 8.50 |
P6 cycles | 11.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 25.28 |
Stall cycles (UFS) | 0.24 |
Nb insns | 96.00 |
Nb uops | 98.00 |
Nb loads | 47.00 |
Nb stores | 11.00 |
Nb stack references | 42.00 |
FLOP/cycle | 0.24 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 6.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 32.97 |
Bytes prefetched | 0.00 |
Bytes loaded | 680.00 |
Bytes stored | 136.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 12.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 52.17 |
Vectorization ratio load | 77.42 |
Vectorization ratio store | 54.55 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.09 |
Vector-efficiency ratio all | 22.83 |
Vector-efficiency ratio load | 27.82 |
Vector-efficiency ratio store | 19.32 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 19.57 |
Path / |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:234-270 |
Module | exec |
nb instructions | 71.75 |
nb uops | 73 |
loop length | 422.50 |
used x86 registers | 11.25 |
used mmx registers | 0 |
used xmm registers | 12.50 |
used ymm registers | 7.75 |
used zmm registers | 0 |
nb stack references | 25.25 |
micro-operation queue | 18.44 cycles |
front end | 18.44 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 8.00 | 9.25 | 15.25 | 15.25 | 6.00 | 9.50 | 8.00 | 6.00 |
cycles | 8.00 | 9.25 | 15.25 | 15.25 | 6.00 | 9.50 | 8.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 18.73 |
Stall cycles | 0.06 |
LM full (events) | 0.24 |
Front-end | 18.44 |
Dispatch | 15.38 |
Data deps. | 0.00 |
Overall L1 | 18.44 |
all | 12% |
load | 61% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 52% |
load | 52% |
store | 100% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 63% |
all | 31% |
load | 58% |
store | 27% |
mul | 0% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 20% |
all | 14% |
load | 27% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 22% |
load | 22% |
store | 25% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 18% |
load | 24% |
store | 15% |
mul | 12% |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:234-270 |
Module | exec |
nb instructions | 8 |
nb uops | 7 |
loop length | 33 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 2 |
micro-operation queue | 1.75 cycles |
front end | 1.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 |
cycles | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 1.86 |
Stall cycles | 0.00 |
Front-end | 1.75 |
Dispatch | 1.00 |
Data deps. | 0.00 |
Overall L1 | 1.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RCX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x3,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x20(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 43cb40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
TEST %EDX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 43cbb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:234-270 |
Module | exec |
nb instructions | 62 |
nb uops | 64 |
loop length | 321 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 10 |
used ymm registers | 1 |
used zmm registers | 0 |
nb stack references | 15 |
micro-operation queue | 16.25 cycles |
front end | 16.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 10.50 | 10.50 | 10.00 | 10.00 | 1.00 | 10.50 | 10.50 | 1.00 |
cycles | 10.50 | 10.50 | 10.00 | 10.00 | 1.00 | 10.50 | 10.50 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 16.56 |
Stall cycles | 0.00 |
Front-end | 16.25 |
Dispatch | 10.50 |
Data deps. | 0.00 |
Overall L1 | 16.25 |
all | 21% |
load | 66% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 23% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 22% |
load | 22% |
store | 0% |
mul | 0% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 30% |
all | 16% |
load | 29% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 13% |
all | 15% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 15% |
load | 18% |
store | 12% |
mul | 12% |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RCX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x3,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x20(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 43cb40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
TEST %EDX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 43cbb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x2e0(%RSP,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0x48(%RSP),%XMM0,%XMM21 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM28 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x150(%RSP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x1c0(%RSP,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0x180(%RSP,%RCX,8),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x140(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x148(%RSP),%RAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
VMOVQ %RAX,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPADDQ 0x400(%RSP),%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPADDQ 0x3e0(%RSP),%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPEXTRQ $0x1,%XMM0,%RDX | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVQ %XMM0,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VEXTRACTI128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVQ %XMM0,%RSI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPEXTRQ $0x1,%XMM0,%RBX | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV 0x138(%RSP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R12,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 43d070 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %XMM1,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %XMM3,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %XMM2,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD %R8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RAX,%RBX,8),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RSI,8),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RDX,8),%R11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RCX,8),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RSP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
SUB %R8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x30(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RAX,%R8,8),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%R15,%R8,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x8(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RAX,%R8,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%R8,1),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R15,%RDX,8),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RDX,%R8,8),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 43cbb0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:234-270 |
Module | exec |
nb instructions | 121 |
nb uops | 123 |
loop length | 717 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 20 |
used ymm registers | 15 |
used zmm registers | 0 |
nb stack references | 42 |
micro-operation queue | 31.00 cycles |
front end | 31.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 12.00 | 15.50 | 26.50 | 26.50 | 11.00 | 15.50 | 12.00 | 11.00 |
cycles | 12.00 | 15.50 | 26.50 | 26.50 | 11.00 | 15.50 | 12.00 | 11.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 31.24 |
Stall cycles | 0.00 |
Front-end | 31.00 |
Dispatch | 26.50 |
Data deps. | 0.00 |
Overall L1 | 31.00 |
all | 15% |
load | 50% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 67% |
load | 78% |
store | 100% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
all | 52% |
load | 75% |
store | 54% |
mul | 0% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 15% |
load | 25% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 26% |
load | 27% |
store | 25% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 27% |
all | 22% |
load | 27% |
store | 19% |
mul | 12% |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 19% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RCX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x3,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x20(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 43cb40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
TEST %EDX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 43cbb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x2e0(%RSP,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0x48(%RSP),%XMM0,%XMM21 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM28 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x150(%RSP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x1c0(%RSP,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0x180(%RSP,%RCX,8),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x140(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x148(%RSP),%RAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
VMOVQ %RAX,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPADDQ 0x400(%RSP),%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPADDQ 0x3e0(%RSP),%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPEXTRQ $0x1,%XMM0,%RDX | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVQ %XMM0,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VEXTRACTI128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVQ %XMM0,%RSI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPEXTRQ $0x1,%XMM0,%RBX | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV 0x138(%RSP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R12,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 43d070 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMOVAPD %XMM21,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %YMM20,%YMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %YMM19,%YMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVUPD 0x340(%RSP),%YMM19 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x360(%RSP),%YMM18 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x380(%RSP),%YMM17 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD %XMM0,0xa0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM0,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM1,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM28,0x90(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM28,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM2,0xc0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM2,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM3,0xd0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM3,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM30,0x80(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM30,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RBX,0x50(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RBX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RSI,8),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x60(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RDX,8),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RCX,8),%R11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x18(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x28(%RSP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x8(%RSP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x40(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x3c0(%RSP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x3a0(%RSP),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R12,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP 0x20(%RSP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
VMOVUPD 0x170(%RSP),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x160(%RSP),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x320(%RSP),%YMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x260(%RSP),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x270(%RSP),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x280(%RSP),%XMM22 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2d0(%RSP),%XMM23 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2c0(%RSP),%XMM24 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2b0(%RSP),%XMM25 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2a0(%RSP),%XMM26 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x290(%RSP),%XMM27 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVAPD %YMM20,%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %YMM21,%YMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVUPD 0xa0(%RSP),%XMM21 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x90(%RSP),%XMM28 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x80(%RSP),%XMM30 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0xe0(%RSP),%XMM31 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0xd0(%RSP),%XMM17 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0xc0(%RSP),%XMM18 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x68(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x60(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x58(%RSP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x50(%RSP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 43cbb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 43d085 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
ADD %R8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RAX,%RBX,8),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RSI,8),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RDX,8),%R11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RCX,8),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RSP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
SUB %R8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV 0x30(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RAX,%R8,8),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%R15,%R8,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x8(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RAX,%R8,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%R8,1),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R15,%RDX,8),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%RDX,%R8,8),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 43cbb0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:234-270 |
Module | exec |
nb instructions | 96 |
nb uops | 98 |
loop length | 619 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 20 |
used ymm registers | 15 |
used zmm registers | 0 |
nb stack references | 42 |
micro-operation queue | 24.75 cycles |
front end | 24.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 8.50 | 10.00 | 23.50 | 23.50 | 11.00 | 11.00 | 8.50 | 11.00 |
cycles | 8.50 | 10.00 | 23.50 | 23.50 | 11.00 | 11.00 | 8.50 | 11.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 25.28 |
Stall cycles | 0.24 |
LM full (events) | 0.96 |
Front-end | 24.75 |
Dispatch | 23.50 |
Data deps. | 0.00 |
Overall L1 | 24.75 |
all | 15% |
load | 66% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 67% |
load | 78% |
store | 100% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
all | 52% |
load | 77% |
store | 54% |
mul | 0% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 15% |
load | 29% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 26% |
load | 27% |
store | 25% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 27% |
all | 22% |
load | 27% |
store | 19% |
mul | 12% |
add-sub | 37% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 19% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1(%RCX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x3,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV 0x20(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 43cb40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
TEST %EDX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 43cbb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD 0x2e0(%RSP,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD 0x48(%RSP),%XMM0,%XMM21 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM28 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x150(%RSP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD 0x1c0(%RSP,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD 0x180(%RSP,%RCX,8),%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x140(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
IMUL %RCX,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x148(%RSP),%RAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
VMOVQ %RAX,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VPADDQ 0x400(%RSP),%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPADDQ 0x3e0(%RSP),%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPEXTRQ $0x1,%XMM0,%RDX | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVQ %XMM0,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VEXTRACTI128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVQ %XMM0,%RSI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPEXTRQ $0x1,%XMM0,%RBX | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV 0x138(%RSP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %R12,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 43d070 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
VMOVAPD %XMM21,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %YMM20,%YMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %YMM19,%YMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVUPD 0x340(%RSP),%YMM19 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x360(%RSP),%YMM18 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x380(%RSP),%YMM17 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD %XMM0,0xa0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM0,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM1,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM28,0x90(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM28,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM2,0xc0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM2,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM3,0xd0(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM3,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VMOVUPD %XMM30,0x80(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VBROADCASTSD %XMM30,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
MOV 0x70(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RBX,0x50(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RBX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RSI,8),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x60(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RDX,8),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%RAX,%RCX,8),%R11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x18(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x28(%RSP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x8(%RSP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x40(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x3c0(%RSP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x3a0(%RSP),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %R12,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CMP 0x20(%RSP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
VMOVUPD 0x170(%RSP),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x160(%RSP),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x320(%RSP),%YMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPD 0x260(%RSP),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x270(%RSP),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x280(%RSP),%XMM22 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2d0(%RSP),%XMM23 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2c0(%RSP),%XMM24 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2b0(%RSP),%XMM25 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x2a0(%RSP),%XMM26 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x290(%RSP),%XMM27 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVAPD %YMM20,%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVAPD %YMM21,%YMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVUPD 0xa0(%RSP),%XMM21 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x90(%RSP),%XMM28 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0x80(%RSP),%XMM30 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0xe0(%RSP),%XMM31 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0xd0(%RSP),%XMM17 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVUPD 0xc0(%RSP),%XMM18 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x68(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x60(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x58(%RSP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV 0x50(%RSP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
JE 43cbb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |