Function: _intel_fast_memset | Module: exec | Source: :0-0 | Coverage: 0.01% |
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Function: _intel_fast_memset | Module: exec | Source: :0-0 | Coverage: 0.01% |
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*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x47ebf0 ENDBR64 |
0x47ebf4 MOV 0x74205(%RIP),%RAX |
0x47ebfb TEST %RAX,%RAX |
0x47ebfe JE 47ec02 |
0x47ec00 JMP %RAX |
0x47ec02 JMP 47ec10 |
0x47ec04 NOPW %CS:(%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:207 | exec |
○ | main.extracted.104 | stl_vector.h:1126 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | main | miniqmc.cpp:404 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 5 |
nb uops | 4 |
loop length | 18 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 1.00 cycles |
front end | 1.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 0.50 | 1.00 | 0.00 |
cycles | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 0.50 | 1.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 1.09 |
Stall cycles | 0.00 |
Front-end | 1.00 |
Dispatch | 1.00 |
Overall L1 | 1.00 |
Source file and lines | |
Module | exec |
nb instructions | 5 |
nb uops | 4 |
loop length | 18 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 1.00 cycles |
front end | 1.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 0.50 | 1.00 | 0.00 |
cycles | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 0.50 | 1.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 1.09 |
Stall cycles | 0.00 |
Front-end | 1.00 |
Dispatch | 1.00 |
Overall L1 | 1.00 |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||
MOV 0x74205(%RIP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %RAX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 47ec02 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 2 |
Source file and lines | |
Module | exec |
nb instructions | 5 |
nb uops | 4 |
loop length | 18 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 1.00 cycles |
front end | 1.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 0.50 | 1.00 | 0.00 |
cycles | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 0.50 | 1.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 1.09 |
Stall cycles | 0.00 |
Front-end | 1.00 |
Dispatch | 1.00 |
Overall L1 | 1.00 |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||
MOV 0x74205(%RIP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
TEST %RAX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 47ec02 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
JMP 47ec10 <__real_memset_impl_setup> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Name | Coverage (%) | Time (s) |
---|---|---|
○_intel_fast_memset | 0.01 | 0 |