Loop Id: 836 | Module: exec | Source: MultiBsplineRef.hpp:284-295 | Coverage: 0.52% |
---|
Loop Id: 836 | Module: exec | Source: MultiBsplineRef.hpp:284-295 | Coverage: 0.52% |
---|
0x43d2e0 VMULPD 0x20(%R10,%RCX,8),%YMM6,%YMM15 [6] |
0x43d2e7 VMULPD (%R10,%RCX,8),%YMM6,%YMM16 [6] |
0x43d2ee VMOVUPD %YMM16,(%R10,%RCX,8) [6] |
0x43d2f5 VMOVUPD %YMM15,0x20(%R10,%RCX,8) [6] |
0x43d2fc VMULPD 0x20(%R13,%RCX,8),%YMM7,%YMM15 [8] |
0x43d303 VMULPD (%R13,%RCX,8),%YMM7,%YMM16 [8] |
0x43d30b VMOVUPD %YMM16,(%R13,%RCX,8) [8] |
0x43d313 VMOVUPD %YMM15,0x20(%R13,%RCX,8) [8] |
0x43d31a VMULPD 0x20(%R12,%RCX,8),%YMM8,%YMM15 [3] |
0x43d321 VMULPD (%R12,%RCX,8),%YMM8,%YMM16 [3] |
0x43d328 VMOVUPD %YMM16,(%R12,%RCX,8) [3] |
0x43d32f VMOVUPD %YMM15,0x20(%R12,%RCX,8) [3] |
0x43d336 VMULPD 0x20(%R11,%RCX,8),%YMM9,%YMM15 [1] |
0x43d33d VMULPD (%R11,%RCX,8),%YMM9,%YMM16 [1] |
0x43d344 VMOVUPD %YMM16,(%R11,%RCX,8) [1] |
0x43d34b VMOVUPD %YMM15,0x20(%R11,%RCX,8) [1] |
0x43d352 VMULPD 0x20(%RDX,%RCX,8),%YMM10,%YMM15 [9] |
0x43d358 VMULPD (%RDX,%RCX,8),%YMM10,%YMM16 [9] |
0x43d35f VMOVUPD %YMM16,(%RDX,%RCX,8) [9] |
0x43d366 VMOVUPD %YMM15,0x20(%RDX,%RCX,8) [9] |
0x43d36c VMULPD 0x20(%R9,%RCX,8),%YMM11,%YMM15 [7] |
0x43d373 VMULPD (%R9,%RCX,8),%YMM11,%YMM16 [7] |
0x43d37a VMOVUPD %YMM16,(%R9,%RCX,8) [7] |
0x43d381 VMOVUPD %YMM15,0x20(%R9,%RCX,8) [7] |
0x43d388 VMULPD 0x20(%RAX,%RCX,8),%YMM12,%YMM15 [4] |
0x43d38e VMULPD (%RAX,%RCX,8),%YMM12,%YMM16 [4] |
0x43d395 VMOVUPD %YMM16,(%RAX,%RCX,8) [4] |
0x43d39c VMOVUPD %YMM15,0x20(%RAX,%RCX,8) [4] |
0x43d3a2 VMULPD 0x20(%RDI,%RCX,8),%YMM13,%YMM15 [5] |
0x43d3a8 VMULPD (%RDI,%RCX,8),%YMM13,%YMM16 [5] |
0x43d3af VMOVUPD %YMM16,(%RDI,%RCX,8) [5] |
0x43d3b6 VMOVUPD %YMM15,0x20(%RDI,%RCX,8) [5] |
0x43d3bc VMULPD 0x20(%R8,%RCX,8),%YMM14,%YMM15 [2] |
0x43d3c3 VMULPD (%R8,%RCX,8),%YMM14,%YMM16 [2] |
0x43d3ca VMOVUPD %YMM16,(%R8,%RCX,8) [2] |
0x43d3d1 VMOVUPD %YMM15,0x20(%R8,%RCX,8) [2] |
0x43d3d8 ADD $0x8,%RCX |
0x43d3dc CMP %RSI,%RCX |
0x43d3df JL 43d2e0 |
/home/kcamus/qaas_runs/169-390-4082/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 284 - 295 |
-------------------------------------------------------------------------------- |
284: #pragma omp simd simdlen(simdlen_) |
285: for (int n = 0; n < num_splines; n++) |
286: { |
287: gx[n] *= dxInv; |
288: gy[n] *= dyInv; |
289: gz[n] *= dzInv; |
290: hxx[n] *= dxx; |
291: hyy[n] *= dyy; |
292: hzz[n] *= dzz; |
293: hxy[n] *= dxy; |
294: hxz[n] *= dxz; |
295: hyz[n] *= dyz; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | miniqmcreference::DiracDetermi[...] | DiracDeterminantRef.cpp:100 | exec |
○ | qmcplusplus::WaveFunction::rat[...] | WaveFunction.cpp:202 | exec |
○ | main.extracted.104 | refwrap.h:347 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | main | miniqmc.cpp:404 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.29 |
Bottlenecks | P4, |
Function | miniqmcreference::einspline_spo_ref |
Source | MultiBsplineRef.hpp:284-295 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 18.00 |
CQA cycles if no scalar integer | 18.00 |
CQA cycles if FP arith vectorized | 18.00 |
CQA cycles if fully vectorized | 9.00 |
Front-end cycles | 14.00 |
DIV/SQRT cycles | 9.00 |
P0 cycles | 9.00 |
P1 cycles | 12.00 |
P2 cycles | 12.00 |
P3 cycles | 18.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 12.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 18.16 |
Stall cycles (UFS) | 3.73 |
Nb insns | 39.00 |
Nb uops | 38.00 |
Nb loads | 18.00 |
Nb stores | 18.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 72.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 64.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 576.00 |
Bytes stored | 576.00 |
Stride 0 | 0.00 |
Stride 1 | 9.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.29 |
Bottlenecks | P4, |
Function | miniqmcreference::einspline_spo_ref |
Source | MultiBsplineRef.hpp:284-295 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 18.00 |
CQA cycles if no scalar integer | 18.00 |
CQA cycles if FP arith vectorized | 18.00 |
CQA cycles if fully vectorized | 9.00 |
Front-end cycles | 14.00 |
DIV/SQRT cycles | 9.00 |
P0 cycles | 9.00 |
P1 cycles | 12.00 |
P2 cycles | 12.00 |
P3 cycles | 18.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 12.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 18.16 |
Stall cycles (UFS) | 3.73 |
Nb insns | 39.00 |
Nb uops | 38.00 |
Nb loads | 18.00 |
Nb stores | 18.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 72.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 64.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 576.00 |
Bytes stored | 576.00 |
Stride 0 | 0.00 |
Stride 1 | 9.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:284-295 |
Module | exec |
nb instructions | 39 |
nb uops | 38 |
loop length | 261 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 11 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 14.00 cycles |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 9.00 | 9.00 | 12.00 | 12.00 | 18.00 | 1.00 | 1.00 | 12.00 |
cycles | 9.00 | 9.00 | 12.00 | 12.00 | 18.00 | 1.00 | 1.00 | 12.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 18.16 |
Stall cycles | 3.73 |
SB full (events) | 7.46 |
Front-end | 14.00 |
Dispatch | 18.00 |
Data deps. | 1.00 |
Overall L1 | 18.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMULPD 0x20(%R10,%RCX,8),%YMM6,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R10,%RCX,8),%YMM6,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R10,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R10,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R13,%RCX,8),%YMM7,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R13,%RCX,8),%YMM7,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R13,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R13,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R12,%RCX,8),%YMM8,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R12,%RCX,8),%YMM8,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R12,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R12,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R11,%RCX,8),%YMM9,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R11,%RCX,8),%YMM9,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R11,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R11,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%RDX,%RCX,8),%YMM10,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RDX,%RCX,8),%YMM10,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%RDX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%RDX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R9,%RCX,8),%YMM11,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R9,%RCX,8),%YMM11,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R9,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R9,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%RAX,%RCX,8),%YMM12,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RAX,%RCX,8),%YMM12,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%RAX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%RAX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%RDI,%RCX,8),%YMM13,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RDI,%RCX,8),%YMM13,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%RDI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%RDI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R8,%RCX,8),%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R8,%RCX,8),%YMM14,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R8,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R8,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x8,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RSI,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JL 43d2e0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | miniqmcreference::einspline_spo_ref |
Source file and lines | MultiBsplineRef.hpp:284-295 |
Module | exec |
nb instructions | 39 |
nb uops | 38 |
loop length | 261 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 11 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 14.00 cycles |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 9.00 | 9.00 | 12.00 | 12.00 | 18.00 | 1.00 | 1.00 | 12.00 |
cycles | 9.00 | 9.00 | 12.00 | 12.00 | 18.00 | 1.00 | 1.00 | 12.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 18.16 |
Stall cycles | 3.73 |
SB full (events) | 7.46 |
Front-end | 14.00 |
Dispatch | 18.00 |
Data deps. | 1.00 |
Overall L1 | 18.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | 50% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMULPD 0x20(%R10,%RCX,8),%YMM6,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R10,%RCX,8),%YMM6,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R10,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R10,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R13,%RCX,8),%YMM7,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R13,%RCX,8),%YMM7,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R13,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R13,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R12,%RCX,8),%YMM8,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R12,%RCX,8),%YMM8,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R12,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R12,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R11,%RCX,8),%YMM9,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R11,%RCX,8),%YMM9,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R11,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R11,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%RDX,%RCX,8),%YMM10,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RDX,%RCX,8),%YMM10,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%RDX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%RDX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R9,%RCX,8),%YMM11,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R9,%RCX,8),%YMM11,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R9,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R9,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%RAX,%RCX,8),%YMM12,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RAX,%RCX,8),%YMM12,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%RAX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%RAX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%RDI,%RCX,8),%YMM13,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%RDI,%RCX,8),%YMM13,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%RDI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%RDI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMULPD 0x20(%R8,%RCX,8),%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD (%R8,%RCX,8),%YMM14,%YMM16 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM16,(%R8,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPD %YMM15,0x20(%R8,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x8,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %RSI,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JL 43d2e0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |