Function: quicksort | Module: exec | Source: :0-0 | Coverage: 0.37% |
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Function: quicksort | Module: exec | Source: :0-0 | Coverage: 0.37% |
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*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x4d8b00 PUSH %RBP |
0x4d8b01 PUSH %R15 |
0x4d8b03 PUSH %R14 |
0x4d8b05 PUSH %R13 |
0x4d8b07 PUSH %R12 |
0x4d8b09 PUSH %RBX |
0x4d8b0a PUSH %RAX |
0x4d8b0b CMP %EDX,%ESI |
0x4d8b0d JGE 4d8bb7 |
0x4d8b13 MOV %EDX,%R15D |
0x4d8b16 MOV %RDI,%R13 |
0x4d8b19 MOVSXD %EDX,%R14 |
0x4d8b1c MOV %R14,%R12 |
0x4d8b1f SAL $0x4,%R12 |
0x4d8b23 ADD %RDI,%R12 |
0x4d8b26 JMP 4d8b64 |
0x4d8b28 NOPL (%RAX,%RAX,1) |
(1949) 0x4d8b30 MOVSXD %EBX,%RBX |
(1949) 0x4d8b33 MOV %RBX,%RAX |
(1949) 0x4d8b36 SAL $0x4,%RAX |
(1949) 0x4d8b3a MOVUPS (%R12),%XMM0 |
(1949) 0x4d8b3f MOVUPS (%R13,%RAX,1),%XMM1 |
(1949) 0x4d8b45 MOVUPS %XMM1,(%R12) |
(1949) 0x4d8b4a MOVUPS %XMM0,(%R13,%RAX,1) |
(1949) 0x4d8b50 LEA -0x1(%RBX),%EDX |
(1949) 0x4d8b53 MOV %R13,%RDI |
(1949) 0x4d8b56 CALL 4d8b00 <quicksort> |
(1949) 0x4d8b5b INC %EBX |
(1949) 0x4d8b5d MOV %EBX,%ESI |
(1949) 0x4d8b5f CMP %R15D,%EBX |
(1949) 0x4d8b62 JGE 4d8bb7 |
(1949) 0x4d8b64 MOVSXD %ESI,%RAX |
(1949) 0x4d8b67 MOV %R14,%RCX |
(1949) 0x4d8b6a SUB %RAX,%RCX |
(1949) 0x4d8b6d SAL $0x4,%RAX |
(1949) 0x4d8b71 ADD %R13,%RAX |
(1949) 0x4d8b74 MOV %ESI,%EBX |
(1949) 0x4d8b76 JMP 4d8b89 |
0x4d8b78 NOPL (%RAX,%RAX,1) |
(1950) 0x4d8b80 ADD $0x10,%RAX |
(1950) 0x4d8b84 DEC %RCX |
(1950) 0x4d8b87 JE 4d8b30 |
(1950) 0x4d8b89 MOV (%RAX),%RDI |
(1950) 0x4d8b8c CMP (%R12),%RDI |
(1950) 0x4d8b90 JAE 4d8b80 |
(1950) 0x4d8b92 MOVSXD %EBX,%RBX |
(1950) 0x4d8b95 MOV 0x8(%RAX),%RBP |
(1950) 0x4d8b99 MOV %RBX,%RDX |
(1950) 0x4d8b9c SAL $0x4,%RDX |
(1950) 0x4d8ba0 MOVUPS (%R13,%RDX,1),%XMM0 |
(1950) 0x4d8ba6 MOVUPS %XMM0,(%RAX) |
(1950) 0x4d8ba9 MOV %RDI,(%R13,%RDX,1) |
(1950) 0x4d8bae MOV %RBP,0x8(%R13,%RDX,1) |
(1950) 0x4d8bb3 INC %EBX |
(1950) 0x4d8bb5 JMP 4d8b80 |
0x4d8bb7 ADD $0x8,%RSP |
0x4d8bbb POP %RBX |
0x4d8bbc POP %R12 |
0x4d8bbe POP %R13 |
0x4d8bc0 POP %R14 |
0x4d8bc2 POP %R15 |
0x4d8bc4 POP %RBP |
0x4d8bc5 RET |
0x4d8bc6 NOPW %CS:(%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►3.23+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | void Kripke::DispatchHelper<Kr[...] | internal.hpp:345 | exec |
○ | Kripke::Kernel::sweepSubdomain[...] | ArchLayout.h:145 | exec |
○ | Kripke::SweepSolver(Kripke::Co[...] | SweepSolver.cpp:78 | exec |
○ | Kripke::SteadyStateSolver(Krip[...] | stl_vector.h:366 | exec |
○ | main | kripke.cpp:482 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 81 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.75 cycles |
front end | 6.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 4.67 | 4.67 | 7.00 | 2.00 | 2.00 | 4.67 |
cycles | 2.00 | 2.00 | 4.67 | 4.67 | 7.00 | 2.00 | 2.00 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 7.12 |
Stall cycles | 0.00 |
Front-end | 6.75 |
Dispatch | 7.00 |
Overall L1 | 7.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 10% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RAX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %EDX,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 4d8bb7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOVSXD %EDX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %R14,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SAL $0x4,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
ADD %RDI,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JMP 4d8b64 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x8,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 81 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.75 cycles |
front end | 6.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 4.67 | 4.67 | 7.00 | 2.00 | 2.00 | 4.67 |
cycles | 2.00 | 2.00 | 4.67 | 4.67 | 7.00 | 2.00 | 2.00 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 7.12 |
Stall cycles | 0.00 |
Front-end | 6.75 |
Dispatch | 7.00 |
Overall L1 | 7.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 10% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %RAX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %EDX,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 4d8bb7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOVSXD %EDX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %R14,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
SAL $0x4,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
ADD %RDI,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JMP 4d8b64 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
ADD $0x8,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼quicksort– | 0.37 | 0.16 |
▼Loop 1949 - - exec– | 0.05 | 0.02 |
○Loop 1950 - - exec | 0.24 | 0.1 |