Loop Id: 642 | Module: libkripke.so | Source: forall.hpp:59-59 [...] | Coverage: 12.5% |
---|
Loop Id: 642 | Module: libkripke.so | Source: forall.hpp:59-59 [...] | Coverage: 12.5% |
---|
0x67ab5 VMOVSD (%R12),%XMM4 [13] |
0x67abb MOV -0x48(%RBP),%R10 [17] |
0x67abf VMOVSD (%R13),%XMM13 [15] |
0x67ac5 VMOVSD (%RBX),%XMM6 [5] |
0x67ac9 VADDSD %XMM4,%XMM4,%XMM7 |
0x67acd VDIVSD (%R10),%XMM7,%XMM3 [4] |
0x67ad2 VMULSD (%RAX),%XMM3,%XMM9 [14] |
0x67ad6 VMOVSD (%RSI),%XMM5 [6] |
0x67ada VADDSD %XMM13,%XMM13,%XMM14 |
0x67adf VADDSD %XMM6,%XMM6,%XMM1 |
0x67ae3 VDIVSD (%R9),%XMM14,%XMM15 [3] |
0x67ae8 ADD %R15,%R9 |
0x67aeb VFMADD213SD (%R8),%XMM15,%XMM5 [2] |
0x67af0 VDIVSD (%R11),%XMM1,%XMM0 [16] |
0x67af5 VADDSD %XMM3,%XMM0,%XMM8 |
0x67af9 VADDSD (%RDI),%XMM15,%XMM2 [19] |
0x67afd VFMADD132SD (%RDX),%XMM9,%XMM0 [18] |
0x67b02 ADD %R14,%R8 |
0x67b05 ADD %R14,%RDI |
0x67b08 VADDSD %XMM8,%XMM2,%XMM12 |
0x67b0d VADDSD %XMM5,%XMM0,%XMM11 |
0x67b11 VDIVSD %XMM12,%XMM11,%XMM13 |
0x67b16 VMOVSD %XMM13,(%RCX) [10] |
0x67b1a VMOVSD %XMM13,%XMM13,%XMM14 |
0x67b1f VMOVSD %XMM13,%XMM13,%XMM15 |
0x67b24 ADD %R14,%RCX |
0x67b27 VFMSUB213SD (%RSI),%XMM10,%XMM14 [6] |
0x67b2c VMOVSD %XMM14,(%RSI) [6] |
0x67b30 VFMSUB213SD (%RDX),%XMM10,%XMM15 [18] |
0x67b35 VMOVSD %XMM15,(%RDX) [18] |
0x67b39 VFMSUB213SD (%RAX),%XMM10,%XMM13 [14] |
0x67b3e ADD %R15,%RDX |
0x67b41 VMOVSD %XMM13,(%RAX) [14] |
0x67b45 ADD %R15,%RAX |
0x67b48 VMOVSD (%RBX),%XMM0 [5] |
0x67b4c VMOVSD (%RSI),%XMM2 [6] |
0x67b50 VMOVSD (%R12),%XMM3 [13] |
0x67b56 VMOVSD (%R13),%XMM6 [15] |
0x67b5c VADDSD %XMM0,%XMM0,%XMM4 |
0x67b60 VDIVSD (%R11),%XMM4,%XMM8 [16] |
0x67b65 VADDSD %XMM3,%XMM3,%XMM5 |
0x67b69 VDIVSD (%R10),%XMM5,%XMM9 [4] |
0x67b6e VMULSD (%RAX),%XMM9,%XMM12 [9] |
0x67b72 VADDSD %XMM6,%XMM6,%XMM1 |
0x67b76 VADDSD %XMM9,%XMM8,%XMM11 |
0x67b7b VDIVSD (%R9),%XMM1,%XMM7 [12] |
0x67b80 VADDSD (%RDI),%XMM7,%XMM14 [1] |
0x67b84 ADD %R15,%R9 |
0x67b87 VFMADD213SD (%R8),%XMM7,%XMM2 [7] |
0x67b8c VFMADD132SD (%RDX),%XMM12,%XMM8 [11] |
0x67b91 ADD %R14,%R8 |
0x67b94 ADD %R14,%RDI |
0x67b97 VADDSD %XMM11,%XMM14,%XMM15 |
0x67b9c VADDSD %XMM2,%XMM8,%XMM13 |
0x67ba0 VDIVSD %XMM15,%XMM13,%XMM6 |
0x67ba5 VMOVSD %XMM6,(%RCX) [8] |
0x67ba9 VMOVSD %XMM6,%XMM6,%XMM1 |
0x67bad VMOVSD %XMM6,%XMM6,%XMM7 |
0x67bb1 ADD %R14,%RCX |
0x67bb4 VFMSUB213SD (%RSI),%XMM10,%XMM1 [6] |
0x67bb9 VMOVSD %XMM1,(%RSI) [6] |
0x67bbd VFMSUB213SD (%RDX),%XMM10,%XMM7 [11] |
0x67bc2 MOV -0x40(%RBP),%R10 [17] |
0x67bc6 ADDQ $0x2,-0x38(%RBP) [17] |
0x67bcb VMOVSD %XMM7,(%RDX) [11] |
0x67bcf VFMSUB213SD (%RAX),%XMM10,%XMM6 [9] |
0x67bd4 ADD %R15,%RDX |
0x67bd7 VMOVSD %XMM6,(%RAX) [9] |
0x67bdb ADD %R15,%RAX |
0x67bde CMP %R10,-0x38(%RBP) [17] |
0x67be2 JNE 67ab5 |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 304 - 304 |
-------------------------------------------------------------------------------- |
304: RAJA_HOST_DEVICE constexpr Ret operator()(const Arg1& lhs, |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105 |
-------------------------------------------------------------------------------- |
87: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
88: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
89: double zcos_dzk = 2.0 * zcos(d) / dz(k); |
90: |
91: Zone z(zone_layout(*i, *j, *k)); |
92: |
93: /* Calculate new zonal flux */ |
94: double psi_d_g_z = (rhs(d,g,z) |
95: + psi_lf(d, g, j, k) * xcos_dxi |
96: + psi_fr(d, g, i, k) * ycos_dyj |
97: + psi_bo(d, g, i, j) * zcos_dzk) |
98: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
99: |
100: psi(d, g, z) = psi_d_g_z; |
101: |
102: /* Apply diamond-difference relationships */ |
103: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
104: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
105: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 107 - 107 |
-------------------------------------------------------------------------------- |
107: RAJA_HOST_DEVICE RAJA_INLINE value_type &operator()(Args... args) const |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.80 |
Bottlenecks | P0, |
Function | void RAJA::internal::StatementExecutor |
Source | forall.hpp:59-59,Operators.hpp:304-304,SweepSubdomain.cpp:87-105,View.hpp:107-107 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 16.00 |
Front-end cycles | 17.75 |
DIV/SQRT cycles | 17.00 |
P0 cycles | 17.00 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 9.00 |
P4 cycles | 9.00 |
P5 cycles | 9.00 |
P6 cycles | 9.00 |
P7 cycles | 32.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 32.49 - 32.79 |
Stall cycles (UFS) | 14.36 - 14.66 |
Nb insns | 71.00 |
Nb uops | 71.00 |
Nb loads | 32.00 |
Nb stores | 9.00 |
Nb stack references | 3.00 |
FLOP/cycle | 1.38 |
Nb FLOP add-sub | 14.00 |
Nb FLOP mul | 2.00 |
Nb FLOP fma | 10.00 |
Nb FLOP div | 8.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.25 |
Bytes prefetched | 0.00 |
Bytes loaded | 256.00 |
Bytes stored | 72.00 |
Stride 0 | 6.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 6.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.80 |
Bottlenecks | P0, |
Function | void RAJA::internal::StatementExecutor |
Source | forall.hpp:59-59,Operators.hpp:304-304,SweepSubdomain.cpp:87-105,View.hpp:107-107 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 16.00 |
Front-end cycles | 17.75 |
DIV/SQRT cycles | 17.00 |
P0 cycles | 17.00 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 9.00 |
P4 cycles | 9.00 |
P5 cycles | 9.00 |
P6 cycles | 9.00 |
P7 cycles | 32.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 32.49 - 32.79 |
Stall cycles (UFS) | 14.36 - 14.66 |
Nb insns | 71.00 |
Nb uops | 71.00 |
Nb loads | 32.00 |
Nb stores | 9.00 |
Nb stack references | 3.00 |
FLOP/cycle | 1.38 |
Nb FLOP add-sub | 14.00 |
Nb FLOP mul | 2.00 |
Nb FLOP fma | 10.00 |
Nb FLOP div | 8.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.25 |
Bytes prefetched | 0.00 |
Bytes loaded | 256.00 |
Bytes stored | 72.00 |
Stride 0 | 6.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 6.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 12.50 |
Path / |
nb instructions | 71 |
nb uops | 71 |
loop length | 307 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 3 |
ADD-SUB / MUL ratio | 7.00 |
micro-operation queue | 17.75 cycles |
front end | 17.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 17.00 | 17.00 | 16.00 | 16.00 | 9.00 | 9.00 | 9.00 | 9.00 |
cycles | 17.00 | 17.00 | 16.00 | 16.00 | 9.00 | 9.00 | 9.00 | 9.00 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 32.49-32.79 |
Stall cycles | 14.36-14.66 |
RS full (events) | 0.03 |
LB full (events) | 18.10-18.40 |
Front-end | 17.75 |
Dispatch | 17.00 |
DIV/SQRT | 32.00 |
Data deps. | 2.00 |
Overall L1 | 32.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R12),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x48(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%R13),%XMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RBX),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VADDSD %XMM4,%XMM4,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R10),%XMM7,%XMM3 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMULSD (%RAX),%XMM3,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD (%RSI),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VADDSD %XMM13,%XMM13,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM6,%XMM6,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R9),%XMM14,%XMM15 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
ADD %R15,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMADD213SD (%R8),%XMM15,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R11),%XMM1,%XMM0 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VADDSD %XMM3,%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD (%RDI),%XMM15,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD (%RDX),%XMM9,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R14,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %R14,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VADDSD %XMM8,%XMM2,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM5,%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD %XMM12,%XMM11,%XMM13 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMOVSD %XMM13,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD %XMM13,%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM13,%XMM13,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
ADD %R14,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMSUB213SD (%RSI),%XMM10,%XMM14 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM14,(%RSI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RDX),%XMM10,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM15,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RAX),%XMM10,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM13,(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD %R15,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD (%RBX),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RSI),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%R12),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%R13),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VADDSD %XMM0,%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R11),%XMM4,%XMM8 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VADDSD %XMM3,%XMM3,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R10),%XMM5,%XMM9 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMULSD (%RAX),%XMM9,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM6,%XMM6,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM9,%XMM8,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R9),%XMM1,%XMM7 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VADDSD (%RDI),%XMM7,%XMM14 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R15,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMADD213SD (%R8),%XMM7,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD (%RDX),%XMM12,%XMM8 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R14,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %R14,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VADDSD %XMM11,%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM2,%XMM8,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD %XMM15,%XMM13,%XMM6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMOVSD %XMM6,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD %XMM6,%XMM6,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM6,%XMM6,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
ADD %R14,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMSUB213SD (%RSI),%XMM10,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM1,(%RSI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RDX),%XMM10,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADDQ $0x2,-0x38(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
VMOVSD %XMM7,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RAX),%XMM10,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM6,(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD %R15,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R10,-0x38(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 67ab5 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0+0xdc5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
nb instructions | 71 |
nb uops | 71 |
loop length | 307 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 3 |
ADD-SUB / MUL ratio | 7.00 |
micro-operation queue | 17.75 cycles |
front end | 17.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 17.00 | 17.00 | 16.00 | 16.00 | 9.00 | 9.00 | 9.00 | 9.00 |
cycles | 17.00 | 17.00 | 16.00 | 16.00 | 9.00 | 9.00 | 9.00 | 9.00 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 32.49-32.79 |
Stall cycles | 14.36-14.66 |
RS full (events) | 0.03 |
LB full (events) | 18.10-18.40 |
Front-end | 17.75 |
Dispatch | 17.00 |
DIV/SQRT | 32.00 |
Data deps. | 2.00 |
Overall L1 | 32.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R12),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x48(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%R13),%XMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RBX),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VADDSD %XMM4,%XMM4,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R10),%XMM7,%XMM3 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMULSD (%RAX),%XMM3,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD (%RSI),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VADDSD %XMM13,%XMM13,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM6,%XMM6,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R9),%XMM14,%XMM15 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
ADD %R15,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMADD213SD (%R8),%XMM15,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R11),%XMM1,%XMM0 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VADDSD %XMM3,%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD (%RDI),%XMM15,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD (%RDX),%XMM9,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R14,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %R14,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VADDSD %XMM8,%XMM2,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM5,%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD %XMM12,%XMM11,%XMM13 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMOVSD %XMM13,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD %XMM13,%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM13,%XMM13,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
ADD %R14,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMSUB213SD (%RSI),%XMM10,%XMM14 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM14,(%RSI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RDX),%XMM10,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM15,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RAX),%XMM10,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM13,(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD %R15,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD (%RBX),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%RSI),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%R12),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSD (%R13),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VADDSD %XMM0,%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R11),%XMM4,%XMM8 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VADDSD %XMM3,%XMM3,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R10),%XMM5,%XMM9 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMULSD (%RAX),%XMM9,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM6,%XMM6,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM9,%XMM8,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD (%R9),%XMM1,%XMM7 | 1 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VADDSD (%RDI),%XMM7,%XMM14 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R15,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMADD213SD (%R8),%XMM7,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD (%RDX),%XMM12,%XMM8 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R14,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %R14,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VADDSD %XMM11,%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM2,%XMM8,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD %XMM15,%XMM13,%XMM6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-14 | 4 |
VMOVSD %XMM6,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSD %XMM6,%XMM6,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
VMOVSD %XMM6,%XMM6,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
ADD %R14,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VFMSUB213SD (%RSI),%XMM10,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM1,(%RSI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RDX),%XMM10,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x40(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADDQ $0x2,-0x38(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
VMOVSD %XMM7,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMSUB213SD (%RAX),%XMM10,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %R15,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSD %XMM6,(%RAX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD %R15,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
CMP %R10,-0x38(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 67ab5 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0.lto_priv.0+0xdc5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Metric | run_0 |
---|---|
Coverage (% app. time) | 12.5 |
Time (s) | 3.87 |
Instance Count | 15728640 |
Iteration Count - min | 8 |
Iteration Count - avg | 8 |
Iteration Count - max | 8 |
Cycles per Iteration - min | 48.75 |
Cycles per Iteration - avg | 55.85 |
Cycles per Iteration - max | 95739.75 |