Function: __svml_i64rem4_l9 | Module: exec | Source: :0-0 | Coverage: 0.04% |
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Function: __svml_i64rem4_l9 | Module: exec | Source: :0-0 | Coverage: 0.04% |
---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x4d2bc0 ENDBR64 |
0x4d2bc4 VPXOR %XMM7,%XMM7,%XMM7 |
0x4d2bc8 VPCMPEQQ %YMM7,%YMM1,%YMM2 |
0x4d2bcd VMOVMSKPD %YMM2,%EAX |
0x4d2bd1 TEST %EAX,%EAX |
0x4d2bd3 JE 4d2bdc |
0x4d2bd5 MOV $0,%EAX |
0x4d2bda DIV %AL |
0x4d2bdc SUB $0x58,%RSP |
0x4d2be0 VMOVUPS %YMM13,0x20(%RSP) |
0x4d2be6 VMOVUPS %YMM12,(%RSP) |
0x4d2beb VMOVUPS %YMM11,-0x20(%RSP) |
0x4d2bf1 VMOVUPS %YMM10,-0x40(%RSP) |
0x4d2bf7 VMOVUPS %YMM9,-0x60(%RSP) |
0x4d2bfd VMOVUPS %YMM8,-0x80(%RSP) |
0x4d2c03 VPSUBQ %YMM1,%YMM7,%YMM2 |
0x4d2c07 VBLENDVPD %YMM1,%YMM2,%YMM1,%YMM1 |
0x4d2c0d VPBLENDD $-0x56,%YMM7,%YMM1,%YMM2 |
0x4d2c13 VPBROADCASTQ 0x3db64(%RIP),%YMM8 |
0x4d2c1c VPOR %YMM2,%YMM8,%YMM2 |
0x4d2c20 VBROADCASTSD 0x3db5f(%RIP),%YMM9 |
0x4d2c29 VADDPD %YMM2,%YMM9,%YMM2 |
0x4d2c2d VPSRLQ $0x20,%YMM1,%YMM3 |
0x4d2c32 VPBROADCASTQ 0x3db55(%RIP),%YMM10 |
0x4d2c3b VPOR %YMM3,%YMM10,%YMM5 |
0x4d2c3f VBROADCASTSD 0x3db50(%RIP),%YMM13 |
0x4d2c48 VADDPD %YMM5,%YMM13,%YMM6 |
0x4d2c4c VADDPD %YMM2,%YMM6,%YMM11 |
0x4d2c50 VBROADCASTSD 0x3db47(%RIP),%YMM5 |
0x4d2c59 VANDPD %YMM5,%YMM11,%YMM5 |
0x4d2c5d VSUBPD %YMM5,%YMM6,%YMM6 |
0x4d2c61 VADDPD %YMM6,%YMM2,%YMM6 |
0x4d2c65 VPCMPGTQ %YMM0,%YMM7,%YMM2 |
0x4d2c6a VPSUBQ %YMM0,%YMM7,%YMM12 |
0x4d2c6e VBLENDVPD %YMM0,%YMM12,%YMM0,%YMM0 |
0x4d2c74 VPSRLQ $0x20,%YMM0,%YMM12 |
0x4d2c79 VPOR %YMM10,%YMM12,%YMM10 |
0x4d2c7e VADDPD %YMM13,%YMM10,%YMM10 |
0x4d2c83 VPBLENDD $-0x56,%YMM7,%YMM0,%YMM7 |
0x4d2c89 VPOR %YMM7,%YMM8,%YMM7 |
0x4d2c8d VADDPD %YMM7,%YMM9,%YMM7 |
0x4d2c91 VADDPD %YMM7,%YMM10,%YMM8 |
0x4d2c95 VCVTPD2PS %YMM11,%XMM4 |
0x4d2c9a VRCPPS %XMM4,%XMM4 |
0x4d2c9e VCVTPS2PD %XMM4,%YMM4 |
0x4d2ca2 VBROADCASTSD 0x3dafd(%RIP),%YMM9 |
0x4d2cab VFNMADD231PD %YMM11,%YMM4,%YMM9 |
0x4d2cb0 VFMADD132PD %YMM4,%YMM4,%YMM9 |
0x4d2cb5 VMULPD %YMM9,%YMM8,%YMM4 |
0x4d2cba VROUNDPD $0x3,%YMM4,%YMM4 |
0x4d2cc0 VBROADCASTSD 0x3dae7(%RIP),%YMM8 |
0x4d2cc9 VANDPD %YMM4,%YMM8,%YMM4 |
0x4d2ccd VFNMADD231PD %YMM4,%YMM5,%YMM10 |
0x4d2cd2 VFNMADD231PD %YMM4,%YMM6,%YMM7 |
0x4d2cd7 VADDPD %YMM7,%YMM10,%YMM7 |
0x4d2cdb VMULPD %YMM7,%YMM9,%YMM10 |
0x4d2cdf VROUNDPD $0x3,%YMM10,%YMM10 |
0x4d2ce5 VANDPD %YMM8,%YMM10,%YMM10 |
0x4d2cea VFNMADD231PD %YMM10,%YMM5,%YMM7 |
0x4d2cef VFNMADD231PD %YMM10,%YMM6,%YMM7 |
0x4d2cf4 VMULPD %YMM7,%YMM9,%YMM11 |
0x4d2cf8 VROUNDPD $0x3,%YMM11,%YMM11 |
0x4d2cfe VANDPD %YMM8,%YMM11,%YMM8 |
0x4d2d03 VFNMADD231PD %YMM5,%YMM8,%YMM7 |
0x4d2d08 VFNMADD231PD %YMM6,%YMM8,%YMM7 |
0x4d2d0d VMULPD %YMM7,%YMM9,%YMM5 |
0x4d2d11 VBROADCASTSD 0x3da66(%RIP),%YMM6 |
0x4d2d1a VADDPD %YMM6,%YMM8,%YMM7 |
0x4d2d1e VADDPD %YMM6,%YMM10,%YMM8 |
0x4d2d22 VBROADCASTSD 0x3da8d(%RIP),%YMM9 |
0x4d2d2b VANDPD %YMM9,%YMM8,%YMM8 |
0x4d2d30 VBROADCASTSD 0x3da57(%RIP),%YMM9 |
0x4d2d39 VADDPD %YMM4,%YMM9,%YMM9 |
0x4d2d3d VPSLLQ $0x20,%YMM9,%YMM10 |
0x4d2d43 VADDPD %YMM13,%YMM9,%YMM9 |
0x4d2d48 VSUBPD %YMM9,%YMM4,%YMM4 |
0x4d2d4d VADDPD %YMM6,%YMM4,%YMM4 |
0x4d2d51 VPSHUFB 0x3da66(%RIP),%YMM4,%YMM4 |
0x4d2d5a VPADDD %YMM4,%YMM10,%YMM4 |
0x4d2d5e VPADDQ %YMM4,%YMM8,%YMM4 |
0x4d2d62 VCVTTPD2DQ %YMM5,%XMM5 |
0x4d2d66 VPMOVZXDQ %XMM5,%YMM5 |
0x4d2d6b VANDPD 0x3da6d(%RIP),%YMM7,%YMM6 |
0x4d2d73 VPADDD %YMM5,%YMM6,%YMM5 |
0x4d2d77 VPADDQ %YMM4,%YMM5,%YMM4 |
0x4d2d7b VPSRLQ $0x20,%YMM4,%YMM5 |
0x4d2d80 VPMULUDQ %YMM1,%YMM5,%YMM6 |
0x4d2d84 VPMULUDQ %YMM3,%YMM5,%YMM5 |
0x4d2d88 VPSLLQ $0x20,%YMM5,%YMM5 |
0x4d2d8d VPADDQ %YMM5,%YMM6,%YMM6 |
0x4d2d91 VPMULUDQ %YMM3,%YMM4,%YMM3 |
0x4d2d95 VPADDQ %YMM5,%YMM3,%YMM3 |
0x4d2d99 VPADDQ %YMM3,%YMM6,%YMM3 |
0x4d2d9d VPSLLQ $0x20,%YMM3,%YMM3 |
0x4d2da2 VPMULUDQ %YMM4,%YMM1,%YMM4 |
0x4d2da6 VPADDQ %YMM3,%YMM4,%YMM3 |
0x4d2daa VPSUBQ %YMM3,%YMM0,%YMM0 |
0x4d2dae VPSRLQ $0x3f,%YMM1,%YMM3 |
0x4d2db3 VPSRLQ $0x3f,%YMM0,%YMM4 |
0x4d2db8 VPCMPEQQ %YMM4,%YMM3,%YMM5 |
0x4d2dbd VPCMPGTQ %YMM0,%YMM1,%YMM6 |
0x4d2dc2 VPAND %YMM6,%YMM5,%YMM5 |
0x4d2dc6 VPCMPGTQ %YMM4,%YMM3,%YMM3 |
0x4d2dcb VPOR %YMM3,%YMM5,%YMM3 |
0x4d2dcf VPANDN %YMM1,%YMM3,%YMM1 |
0x4d2dd3 VPSUBQ %YMM1,%YMM0,%YMM0 |
0x4d2dd7 VPXOR %YMM2,%YMM0,%YMM0 |
0x4d2ddb VPSUBQ %YMM2,%YMM0,%YMM0 |
0x4d2ddf VMOVUPS -0x80(%RSP),%YMM8 |
0x4d2de5 VMOVUPS -0x60(%RSP),%YMM9 |
0x4d2deb VMOVUPS -0x40(%RSP),%YMM10 |
0x4d2df1 VMOVUPS -0x20(%RSP),%YMM11 |
0x4d2df7 VMOVUPS (%RSP),%YMM12 |
0x4d2dfc VMOVUPS 0x20(%RSP),%YMM13 |
0x4d2e02 ADD $0x58,%RSP |
0x4d2e06 RET |
0x4d2e07 NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | void Kripke::DispatchHelper<Kr[...] | internal.hpp:345 | exec |
○ | Kripke::Kernel::source(Kripke:[...] | ArchLayout.h:145 | exec |
○ | Kripke::SteadyStateSolver(Krip[...] | basic_string.h:202 | exec |
○ | main | kripke.cpp:482 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 115 |
nb uops | 127.50 |
loop length | 579.50 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 6 |
ADD-SUB / MUL ratio | 3.75 |
micro-operation queue | 31.88 cycles |
front end | 31.88 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 31.00 | 31.00 | 9.00 | 9.00 | 6.00 | 31.00 | 10.50 | 7.00 |
cycles | 31.00 | 31.00 | 9.00 | 9.00 | 6.00 | 31.00 | 10.50 | 7.00 |
Cycles executing div or sqrt instructions | 3.00 |
FE+BE cycles | 185.19-186.38 |
Stall cycles | 153.87-155.06 |
RS full (events) | 176.59-180.34 |
Front-end | 31.88 |
Dispatch | 31.00 |
DIV/SQRT | 3.00 |
Overall L1 | 32.12 |
all | 92% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 88% |
all | 87% |
load | 46% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 65% |
all | 89% |
load | 44% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 78% |
all | 45% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 43% |
all | 44% |
load | 30% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 25% |
other | 35% |
all | 45% |
load | 29% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 25% |
other | 40% |
Source file and lines | |
Module | exec |
nb instructions | 116 |
nb uops | 133 |
loop length | 583 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 6 |
ADD-SUB / MUL ratio | 3.75 |
micro-operation queue | 33.25 cycles |
front end | 33.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 31.00 | 31.00 | 9.00 | 9.00 | 6.00 | 31.00 | 16.00 | 7.00 |
cycles | 31.00 | 31.00 | 9.00 | 9.00 | 6.00 | 31.00 | 16.00 | 7.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 185.13-186.38 |
Stall cycles | 153.30-154.55 |
RS full (events) | 175.80-180.71 |
Front-end | 33.25 |
Dispatch | 31.00 |
DIV/SQRT | 6.00 |
Overall L1 | 33.25 |
all | 91% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 86% |
all | 87% |
load | 46% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 65% |
all | 89% |
load | 44% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 77% |
all | 45% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 42% |
all | 44% |
load | 30% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 25% |
other | 35% |
all | 44% |
load | 29% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 25% |
other | 39% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPCMPEQQ %YMM7,%YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVMSKPD %YMM2,%EAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4d2bdc | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV $0,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
DIV %AL | 10 | 2.50 | 2.50 | 0 | 0 | 0 | 2.50 | 2.50 | 0 | 23 | 6 |
SUB $0x58,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVUPS %YMM13,0x20(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM12,(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM11,-0x20(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM10,-0x40(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM9,-0x60(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM8,-0x80(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VPSUBQ %YMM1,%YMM7,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBLENDVPD %YMM1,%YMM2,%YMM1,%YMM1 | 2 | 0.67 | 0.67 | 0 | 0 | 0 | 0.67 | 0 | 0 | 1-2 | 1 |
VPBLENDD $-0x56,%YMM7,%YMM1,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPBROADCASTQ 0x3db64(%RIP),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPOR %YMM2,%YMM8,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBROADCASTSD 0x3db5f(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM2,%YMM9,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPSRLQ $0x20,%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ 0x3db55(%RIP),%YMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPOR %YMM3,%YMM10,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBROADCASTSD 0x3db50(%RIP),%YMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM5,%YMM13,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM2,%YMM6,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x3db47(%RIP),%YMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VANDPD %YMM5,%YMM11,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VSUBPD %YMM5,%YMM6,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM6,%YMM2,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPCMPGTQ %YMM0,%YMM7,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPSUBQ %YMM0,%YMM7,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBLENDVPD %YMM0,%YMM12,%YMM0,%YMM0 | 2 | 0.67 | 0.67 | 0 | 0 | 0 | 0.67 | 0 | 0 | 1-2 | 1 |
VPSRLQ $0x20,%YMM0,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPOR %YMM10,%YMM12,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %YMM13,%YMM10,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPBLENDD $-0x56,%YMM7,%YMM0,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPOR %YMM7,%YMM8,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %YMM7,%YMM9,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM7,%YMM10,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2PS %YMM11,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 7 | 1 |
VRCPPS %XMM4,%XMM4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VCVTPS2PD %XMM4,%YMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 7 | 1 |
VBROADCASTSD 0x3dafd(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VFNMADD231PD %YMM11,%YMM4,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PD %YMM4,%YMM4,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM9,%YMM8,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x3,%YMM4,%YMM4 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VBROADCASTSD 0x3dae7(%RIP),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VANDPD %YMM4,%YMM8,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VFNMADD231PD %YMM4,%YMM5,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD %YMM4,%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM7,%YMM10,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM7,%YMM9,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x3,%YMM10,%YMM10 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %YMM8,%YMM10,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VFNMADD231PD %YMM10,%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD %YMM10,%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM7,%YMM9,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x3,%YMM11,%YMM11 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %YMM8,%YMM11,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VFNMADD231PD %YMM5,%YMM8,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD %YMM6,%YMM8,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM7,%YMM9,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x3da66(%RIP),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM6,%YMM8,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM6,%YMM10,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x3da8d(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VANDPD %YMM9,%YMM8,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBROADCASTSD 0x3da57(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM4,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPSLLQ $0x20,%YMM9,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDPD %YMM13,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSUBPD %YMM9,%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM6,%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPSHUFB 0x3da66(%RIP),%YMM4,%YMM4 | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 1 | 1 |
VPADDD %YMM4,%YMM10,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM4,%YMM8,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VCVTTPD2DQ %YMM5,%XMM5 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 7 | 1 |
VPMOVZXDQ %XMM5,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VANDPD 0x3da6d(%RIP),%YMM7,%YMM6 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPADDD %YMM5,%YMM6,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM4,%YMM5,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSRLQ $0x20,%YMM4,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMULUDQ %YMM1,%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPMULUDQ %YMM3,%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSLLQ $0x20,%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %YMM5,%YMM6,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPMULUDQ %YMM3,%YMM4,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM5,%YMM3,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM3,%YMM6,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x20,%YMM3,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMULUDQ %YMM4,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM3,%YMM4,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSUBQ %YMM3,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSRLQ $0x3f,%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPSRLQ $0x3f,%YMM0,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPCMPEQQ %YMM4,%YMM3,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPCMPGTQ %YMM0,%YMM1,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPAND %YMM6,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPCMPGTQ %YMM4,%YMM3,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPOR %YMM3,%YMM5,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPANDN %YMM1,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSUBQ %YMM1,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPXOR %YMM2,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSUBQ %YMM2,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VMOVUPS -0x80(%RSP),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS -0x60(%RSP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS -0x40(%RSP),%YMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS -0x20(%RSP),%YMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS (%RSP),%YMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS 0x20(%RSP),%YMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
ADD $0x58,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
Source file and lines | |
Module | exec |
nb instructions | 114 |
nb uops | 122 |
loop length | 576 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 6 |
ADD-SUB / MUL ratio | 3.75 |
micro-operation queue | 30.50 cycles |
front end | 30.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 31.00 | 31.00 | 9.00 | 9.00 | 6.00 | 31.00 | 5.00 | 7.00 |
cycles | 31.00 | 31.00 | 9.00 | 9.00 | 6.00 | 31.00 | 5.00 | 7.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 185.25-186.38 |
Stall cycles | 154.43-155.56 |
RS full (events) | 177.37-179.98 |
Front-end | 30.50 |
Dispatch | 31.00 |
Overall L1 | 31.00 |
all | 93% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 89% |
all | 87% |
load | 46% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 65% |
all | 89% |
load | 44% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 78% |
all | 46% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 44% |
all | 44% |
load | 30% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 25% |
other | 35% |
all | 45% |
load | 29% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 25% |
other | 40% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||
VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VPCMPEQQ %YMM7,%YMM1,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVMSKPD %YMM2,%EAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JE 4d2bdc | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
SUB $0x58,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVUPS %YMM13,0x20(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM12,(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM11,-0x20(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM10,-0x40(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM9,-0x60(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVUPS %YMM8,-0x80(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VPSUBQ %YMM1,%YMM7,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBLENDVPD %YMM1,%YMM2,%YMM1,%YMM1 | 2 | 0.67 | 0.67 | 0 | 0 | 0 | 0.67 | 0 | 0 | 1-2 | 1 |
VPBLENDD $-0x56,%YMM7,%YMM1,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPBROADCASTQ 0x3db64(%RIP),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPOR %YMM2,%YMM8,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBROADCASTSD 0x3db5f(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM2,%YMM9,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPSRLQ $0x20,%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ 0x3db55(%RIP),%YMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPOR %YMM3,%YMM10,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBROADCASTSD 0x3db50(%RIP),%YMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM5,%YMM13,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM2,%YMM6,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x3db47(%RIP),%YMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VANDPD %YMM5,%YMM11,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VSUBPD %YMM5,%YMM6,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM6,%YMM2,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPCMPGTQ %YMM0,%YMM7,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPSUBQ %YMM0,%YMM7,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBLENDVPD %YMM0,%YMM12,%YMM0,%YMM0 | 2 | 0.67 | 0.67 | 0 | 0 | 0 | 0.67 | 0 | 0 | 1-2 | 1 |
VPSRLQ $0x20,%YMM0,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPOR %YMM10,%YMM12,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %YMM13,%YMM10,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPBLENDD $-0x56,%YMM7,%YMM0,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPOR %YMM7,%YMM8,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %YMM7,%YMM9,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM7,%YMM10,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2PS %YMM11,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 7 | 1 |
VRCPPS %XMM4,%XMM4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VCVTPS2PD %XMM4,%YMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 7 | 1 |
VBROADCASTSD 0x3dafd(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VFNMADD231PD %YMM11,%YMM4,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PD %YMM4,%YMM4,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM9,%YMM8,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x3,%YMM4,%YMM4 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VBROADCASTSD 0x3dae7(%RIP),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VANDPD %YMM4,%YMM8,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VFNMADD231PD %YMM4,%YMM5,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD %YMM4,%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM7,%YMM10,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM7,%YMM9,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x3,%YMM10,%YMM10 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %YMM8,%YMM10,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VFNMADD231PD %YMM10,%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD %YMM10,%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM7,%YMM9,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VROUNDPD $0x3,%YMM11,%YMM11 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %YMM8,%YMM11,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VFNMADD231PD %YMM5,%YMM8,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD %YMM6,%YMM8,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM7,%YMM9,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x3da66(%RIP),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM6,%YMM8,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM6,%YMM10,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x3da8d(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VANDPD %YMM9,%YMM8,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VBROADCASTSD 0x3da57(%RIP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VADDPD %YMM4,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPSLLQ $0x20,%YMM9,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDPD %YMM13,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSUBPD %YMM9,%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD %YMM6,%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPSHUFB 0x3da66(%RIP),%YMM4,%YMM4 | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 1 | 1 |
VPADDD %YMM4,%YMM10,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM4,%YMM8,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VCVTTPD2DQ %YMM5,%XMM5 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 7 | 1 |
VPMOVZXDQ %XMM5,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VANDPD 0x3da6d(%RIP),%YMM7,%YMM6 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 |
VPADDD %YMM5,%YMM6,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM4,%YMM5,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSRLQ $0x20,%YMM4,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMULUDQ %YMM1,%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPMULUDQ %YMM3,%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSLLQ $0x20,%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %YMM5,%YMM6,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPMULUDQ %YMM3,%YMM4,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM5,%YMM3,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM3,%YMM6,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x20,%YMM3,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMULUDQ %YMM4,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM3,%YMM4,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSUBQ %YMM3,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSRLQ $0x3f,%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPSRLQ $0x3f,%YMM0,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPCMPEQQ %YMM4,%YMM3,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPCMPGTQ %YMM0,%YMM1,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPAND %YMM6,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPCMPGTQ %YMM4,%YMM3,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
VPOR %YMM3,%YMM5,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPANDN %YMM1,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSUBQ %YMM1,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPXOR %YMM2,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VPSUBQ %YMM2,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
VMOVUPS -0x80(%RSP),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS -0x60(%RSP),%YMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS -0x40(%RSP),%YMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS -0x20(%RSP),%YMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS (%RSP),%YMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
VMOVUPS 0x20(%RSP),%YMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
ADD $0x58,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
Name | Coverage (%) | Time (s) |
---|---|---|
○__svml_i64rem4_l9 | 0.04 | 0.01 |