Loop Id: 1397 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 0.02% |
---|
Loop Id: 1397 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 0.02% |
---|
0x46dea0 MOV -0x78(%RBP),%RDX |
0x46dea4 INC %RDX |
0x46dea7 MOV -0x38(%RBP),%RCX |
0x46deab ADD -0x68(%RBP),%RCX |
0x46deaf MOV -0x70(%RBP),%RAX |
0x46deb3 ADD %RAX,-0xd8(%RBP) |
0x46deba ADD %RAX,-0xd0(%RBP) |
0x46dec1 ADD %RAX,-0xc8(%RBP) |
0x46dec8 MOV %RDX,%RAX |
0x46decb MOV %RDX,-0x78(%RBP) |
0x46decf CMP -0x1c8(%RBP),%RDX |
0x46ded6 JE 46dd50 |
0x46dedc MOV %RCX,-0x38(%RBP) |
0x46dee0 TEST %R14,%R14 |
0x46dee3 JLE 46dea0 |
0x46dee5 MOV -0xb8(%RBP),%RAX |
0x46deec MOV %RAX,%RDX |
0x46deef MOV -0x1b0(%RBP),%RSI |
0x46def6 OR %RSI,%RDX |
0x46def9 SHR $0x20,%RDX |
0x46defd JE 46df10 |
0x46deff CQTO |
0x46df01 IDIV %RSI |
0x46df04 JMP 46df14 |
0x46df10 XOR %EDX,%EDX |
0x46df12 DIV %ESI |
0x46df14 CMP $0x1,%RDX |
0x46df18 SBB $-0x1,%RAX |
0x46df1c MOV -0x78(%RBP),%RDX |
0x46df20 IMUL -0xc0(%RBP),%RDX |
0x46df28 ADD -0x60(%RBP),%RDX |
0x46df2c MOV %RDX,-0x1f8(%RBP) |
0x46df33 IMUL -0x1a8(%RBP),%RDX |
0x46df3b ADD -0x1c0(%RBP),%RDX |
0x46df42 MOV %RDX,-0x1d0(%RBP) |
0x46df49 MOV -0xc8(%RBP),%RDX |
0x46df50 MOV -0xd0(%RBP),%RSI |
0x46df57 MOV -0xd8(%RBP),%RBX |
0x46df5e MOV -0x1b8(%RBP),%RCX |
0x46df65 XOR %EDI,%EDI |
0x46df67 MOV %RDI,-0x30(%RBP) |
0x46df6b MOV %RAX,-0xe8(%RBP) |
0x46df72 JMP 46dfd1 |
(1398) 0x46df80 MOV -0x30(%RBP),%RDX |
(1398) 0x46df84 INC %RDX |
(1398) 0x46df87 MOV %R10,%RCX |
(1398) 0x46df8a ADD -0x88(%RBP),%RCX |
(1398) 0x46df91 MOV -0x90(%RBP),%RAX |
(1398) 0x46df98 MOV -0x48(%RBP),%R8 |
(1398) 0x46df9c ADD %RAX,%R8 |
(1398) 0x46df9f MOV -0x58(%RBP),%RSI |
(1398) 0x46dfa3 ADD %RAX,%RSI |
(1398) 0x46dfa6 MOV -0x50(%RBP),%RDI |
(1398) 0x46dfaa ADD %RAX,%RDI |
(1398) 0x46dfad MOV -0x1e0(%RBP),%R14 |
(1398) 0x46dfb4 MOV %RDX,%RAX |
(1398) 0x46dfb7 MOV %RDX,-0x30(%RBP) |
(1398) 0x46dfbb CMP %R14,%RDX |
(1398) 0x46dfbe MOV -0xe8(%RBP),%RAX |
(1398) 0x46dfc5 MOV %RDI,%RDX |
(1398) 0x46dfc8 MOV %R8,%RBX |
(1398) 0x46dfcb JE 46dea0 |
(1398) 0x46dfd1 MOV %RBX,-0x48(%RBP) |
(1398) 0x46dfd5 MOV %RDX,-0x50(%RBP) |
(1398) 0x46dfd9 MOV %RSI,-0x58(%RBP) |
(1398) 0x46dfdd TEST %RAX,%RAX |
(1398) 0x46dfe0 MOV -0x1f0(%RBP),%RDI |
(1398) 0x46dfe7 MOV %RCX,%R10 |
(1398) 0x46dfea MOV -0x1e8(%RBP),%R14 |
(1398) 0x46dff1 MOV -0x40(%RBP),%RSI |
(1398) 0x46dff5 MOV -0x1f8(%RBP),%RDX |
(1398) 0x46dffc JLE 46df80 |
(1398) 0x46dffe MOV -0x30(%RBP),%R8 |
(1398) 0x46e002 IMUL -0xe0(%RBP),%R8 |
(1398) 0x46e00a ADD -0x80(%RBP),%R8 |
(1398) 0x46e00e MOV -0x1d0(%RBP),%RAX |
(1398) 0x46e015 MOV %R8,-0xa8(%RBP) |
(1398) 0x46e01c ADD %R8,%RAX |
(1398) 0x46e01f MOV %RAX,-0xa0(%RBP) |
(1398) 0x46e026 XOR %R15D,%R15D |
(1398) 0x46e029 XOR %EAX,%EAX |
(1398) 0x46e02b MOV -0xe8(%RBP),%R11 |
(1398) 0x46e032 MOV -0x200(%RBP),%R8 |
(1398) 0x46e039 NOPL (%RAX) |
(1399) 0x46e040 MOV %RDI,%RBX |
(1399) 0x46e043 VMOVSD (%RDI,%RSI,8),%XMM0 |
(1399) 0x46e048 VADDSD %XMM0,%XMM0,%XMM0 |
(1399) 0x46e04c VDIVSD (%R9,%RAX,1),%XMM0,%XMM0 |
(1399) 0x46e052 MOV -0x220(%RBP),%RDI |
(1399) 0x46e059 VMOVSD (%RDI,%RSI,8),%XMM1 |
(1399) 0x46e05e MOV -0x210(%RBP),%RCX |
(1399) 0x46e065 VMOVHPD (%RCX,%RSI,8),%XMM1,%XMM1 |
(1399) 0x46e06a MOV -0xa8(%RBP),%RSI |
(1399) 0x46e071 MOV -0x218(%RBP),%RDI |
(1399) 0x46e078 VMOVSD (%RDI,%RSI,8),%XMM2 |
(1399) 0x46e07d MOV -0x208(%RBP),%RSI |
(1399) 0x46e084 VMOVHPD (%RSI,%RDX,8),%XMM2,%XMM2 |
(1399) 0x46e089 VADDPD %XMM1,%XMM1,%XMM1 |
(1399) 0x46e08d VDIVPD %XMM2,%XMM1,%XMM1 |
(1399) 0x46e091 MOV -0xa0(%RBP),%RCX |
(1399) 0x46e098 VMOVSD (%R8,%RCX,8),%XMM2 |
(1399) 0x46e09e MOV %RBX,%RDI |
(1399) 0x46e0a1 MOV %R10,%R12 |
(1399) 0x46e0a4 MOV -0x50(%RBP),%RSI |
(1399) 0x46e0a8 VFMADD213SD (%RSI,%R15,1),%XMM0,%XMM2 |
(1399) 0x46e0ae MOV -0x38(%RBP),%R10 |
(1399) 0x46e0b2 VFMADD231SD (%R10,%RAX,1),%XMM1,%XMM2 |
(1399) 0x46e0b8 VPERMILPD $0x1,%XMM1,%XMM3 |
(1399) 0x46e0be VFMADD231SD (%R12,%RAX,1),%XMM3,%XMM2 |
(1399) 0x46e0c4 VADDSD %XMM0,%XMM1,%XMM0 |
(1399) 0x46e0c8 MOV -0x58(%RBP),%RSI |
(1399) 0x46e0cc VADDSD (%RSI,%R15,1),%XMM3,%XMM1 |
(1399) 0x46e0d2 MOV -0x48(%RBP),%RSI |
(1399) 0x46e0d6 VADDSD %XMM0,%XMM1,%XMM0 |
(1399) 0x46e0da VDIVSD %XMM0,%XMM2,%XMM0 |
(1399) 0x46e0de VMOVSD %XMM0,(%RSI,%R15,1) |
(1399) 0x46e0e4 VADDSD %XMM0,%XMM0,%XMM0 |
(1399) 0x46e0e8 VSUBSD (%R8,%RCX,8),%XMM0,%XMM1 |
(1399) 0x46e0ee VMOVSD %XMM1,(%R8,%RCX,8) |
(1399) 0x46e0f4 MOV -0x40(%RBP),%RSI |
(1399) 0x46e0f8 VSUBSD (%R10,%RAX,1),%XMM0,%XMM1 |
(1399) 0x46e0fe VMOVSD %XMM1,(%R10,%RAX,1) |
(1399) 0x46e104 VSUBSD (%R12,%RAX,1),%XMM0,%XMM0 |
(1399) 0x46e10a MOV %R12,%R10 |
(1399) 0x46e10d VMOVSD %XMM0,(%R12,%RAX,1) |
(1399) 0x46e113 ADD %R13,%RAX |
(1399) 0x46e116 ADD %R14,%R15 |
(1399) 0x46e119 DEC %R11 |
(1399) 0x46e11c JNE 46e040 |
(1398) 0x46e122 JMP 46df80 |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55 |
-------------------------------------------------------------------------------- |
55: return a * b; |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 250 - 310 |
-------------------------------------------------------------------------------- |
250: return (diff % stride != difference_type{0}) |
[...] |
310: return value_type(val + rhs * stride); |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
/home/kcamus/qaas_runs/169-391-8990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105 |
-------------------------------------------------------------------------------- |
87: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
88: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
[...] |
95: + psi_lf(d, g, j, k) * xcos_dxi |
96: + psi_fr(d, g, i, k) * ycos_dyj |
97: + psi_bo(d, g, i, j) * zcos_dzk) |
98: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
99: |
100: psi(d, g, z) = psi_d_g_z; |
101: |
102: /* Apply diamond-difference relationships */ |
103: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
104: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
105: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_fork_call | libiomp5.so | |
○ | __kmpc_fork_call | libiomp5.so | |
○ | void Kripke::DispatchHelper<Kr[...] | internal.hpp:345 | exec |
○ | Kripke::Kernel::sweepSubdomain[...] | ArchLayout.h:145 | exec |
○ | Kripke::SweepSolver(Kripke::Co[...] | SweepSolver.cpp:78 | exec |
○ | Kripke::SteadyStateSolver(Krip[...] | stl_vector.h:366 | exec |
○ | main | kripke.cpp:482 | exec |
○ | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.22 - 2.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.08 - 3.46 |
Bottlenecks | P0, |
Function | void Kripke::DispatchHelper |
Source | Layout.hpp:55-55,forall.hpp:59-59,Iterators.hpp:250-310,Operators.hpp:307-307,SweepSubdomain.cpp:87-105 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 30.00 - 96.00 |
CQA cycles if no scalar integer | 30.00 - 96.00 |
CQA cycles if FP arith vectorized | 30.00 - 96.00 |
CQA cycles if fully vectorized | 13.50 - 46.50 |
Front-end cycles | 27.75 |
DIV/SQRT cycles | 22.00 |
P0 cycles | 22.00 |
P1 cycles | 9.50 |
P2 cycles | 9.50 |
P3 cycles | 9.00 |
P4 cycles | 22.00 |
P5 cycles | 22.00 |
P6 cycles | 9.00 |
P7 cycles | 30.00 - 96.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 30.37 - 96.37 |
Stall cycles (UFS) | 17.43 - 83.43 |
Nb insns | 43.00 |
Nb uops | 111.00 |
Nb loads | 19.00 |
Nb stores | 9.00 |
Nb stack references | 19.00 |
FLOP/cycle | 0.00 - 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 2.33 - 7.47 |
Bytes prefetched | 0.00 |
Bytes loaded | 152.00 |
Bytes stored | 72.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.02 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 9.38 |
Vector-efficiency ratio other | 11.46 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.22 - 2.06 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.08 - 3.46 |
Bottlenecks | P0, |
Function | void Kripke::DispatchHelper |
Source | Layout.hpp:55-55,forall.hpp:59-59,Iterators.hpp:250-310,Operators.hpp:307-307,SweepSubdomain.cpp:87-105 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 30.00 - 96.00 |
CQA cycles if no scalar integer | 30.00 - 96.00 |
CQA cycles if FP arith vectorized | 30.00 - 96.00 |
CQA cycles if fully vectorized | 13.50 - 46.50 |
Front-end cycles | 27.75 |
DIV/SQRT cycles | 22.00 |
P0 cycles | 22.00 |
P1 cycles | 9.50 |
P2 cycles | 9.50 |
P3 cycles | 9.00 |
P4 cycles | 22.00 |
P5 cycles | 22.00 |
P6 cycles | 9.00 |
P7 cycles | 30.00 - 96.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 30.37 - 96.37 |
Stall cycles (UFS) | 17.43 - 83.43 |
Nb insns | 43.00 |
Nb uops | 111.00 |
Nb loads | 19.00 |
Nb stores | 9.00 |
Nb stack references | 19.00 |
FLOP/cycle | 0.00 - 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 2.33 - 7.47 |
Bytes prefetched | 0.00 |
Bytes loaded | 152.00 |
Bytes stored | 72.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.02 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 9.38 |
Vector-efficiency ratio other | 11.46 |
Path / |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 43 |
nb uops | 111 |
loop length | 202 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 19 |
micro-operation queue | 27.75 cycles |
front end | 27.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 22.00 | 22.00 | 9.50 | 9.50 | 9.00 | 22.00 | 22.00 | 9.00 |
cycles | 22.00 | 22.00 | 9.50 | 9.50 | 9.00 | 22.00 | 22.00 | 9.00 |
Cycles executing div or sqrt instructions | 30.00-96.00 |
FE+BE cycles | 30.37-96.37 |
Stall cycles | 17.43-83.43 |
LB full (events) | 17.93-83.93 |
Front-end | 27.75 |
Dispatch | 22.00 |
DIV/SQRT | 30.00-96.00 |
Overall L1 | 30.00-96.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD -0x68(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD %RAX,-0xd8(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
ADD %RAX,-0xd0(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
ADD %RAX,-0xc8(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP -0x1c8(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 46dd50 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x440> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 46dea0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x590> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x1b0(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
OR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SHR $0x20,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
JE 46df10 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
IDIV %RSI | 57 | 14.25 | 14.25 | 0 | 0 | 0 | 14.25 | 14.25 | 0 | 42-95 | 24-90 |
JMP 46df14 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x604> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
DIV %ESI | 10 | 2.50 | 2.50 | 0 | 0 | 0 | 2.50 | 2.50 | 0 | 26 | 6 |
CMP $0x1,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SBB $-0x1,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV -0x78(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
IMUL -0xc0(%RBP),%RDX | 1 | 0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0x60(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %RDX,-0x1f8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
IMUL -0x1a8(%RBP),%RDX | 1 | 0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0x1c0(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %RDX,-0x1d0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0xc8(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0xd0(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0xd8(%RBP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x1b8(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 46dfd1 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x6c1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 43 |
nb uops | 111 |
loop length | 202 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 19 |
micro-operation queue | 27.75 cycles |
front end | 27.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 22.00 | 22.00 | 9.50 | 9.50 | 9.00 | 22.00 | 22.00 | 9.00 |
cycles | 22.00 | 22.00 | 9.50 | 9.50 | 9.00 | 22.00 | 22.00 | 9.00 |
Cycles executing div or sqrt instructions | 30.00-96.00 |
FE+BE cycles | 30.37-96.37 |
Stall cycles | 17.43-83.43 |
LB full (events) | 17.93-83.93 |
Front-end | 27.75 |
Dispatch | 22.00 |
DIV/SQRT | 30.00-96.00 |
Overall L1 | 30.00-96.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 9% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD -0x68(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
ADD %RAX,-0xd8(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
ADD %RAX,-0xd0(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
ADD %RAX,-0xc8(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP -0x1c8(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JE 46dd50 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x440> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JLE 46dea0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x590> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV -0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x1b0(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
OR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SHR $0x20,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
JE 46df10 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
IDIV %RSI | 57 | 14.25 | 14.25 | 0 | 0 | 0 | 14.25 | 14.25 | 0 | 42-95 | 24-90 |
JMP 46df14 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x604> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
DIV %ESI | 10 | 2.50 | 2.50 | 0 | 0 | 0 | 2.50 | 2.50 | 0 | 26 | 6 |
CMP $0x1,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
SBB $-0x1,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
MOV -0x78(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
IMUL -0xc0(%RBP),%RDX | 1 | 0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0x60(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %RDX,-0x1f8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
IMUL -0x1a8(%RBP),%RDX | 1 | 0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0x1c0(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
MOV %RDX,-0x1d0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0xc8(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0xd0(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0xd8(%RBP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x1b8(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %RDI,-0x30(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RAX,-0xe8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 46dfd1 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x6c1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |