Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 61.38% |
---|
Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 61.38% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-110-4860/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216 |
-------------------------------------------------------------------------------- |
172: #pragma omp parallel for reduction(+:ePot) |
173: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
174: { |
175: int nIBox = s->boxes->nAtoms[iBox]; |
176: |
177: // loop over neighbors of iBox |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
0x4061c0 PUSH %RBP |
0x4061c1 MOV %RSP,%RBP |
0x4061c4 PUSH %R15 |
0x4061c6 PUSH %R14 |
0x4061c8 PUSH %R13 |
0x4061ca PUSH %R12 |
0x4061cc MOV %RDI,%R12 |
0x4061cf PUSH %RBX |
0x4061d0 SUB $0x68,%RSP |
0x4061d4 VMOVSD 0x18(%RDI),%XMM10 |
0x4061d9 VMOVSD 0x10(%RDI),%XMM9 |
0x4061de MOV 0x30(%RDI),%EAX |
0x4061e1 VMOVSD 0x20(%RDI),%XMM5 |
0x4061e6 VMOVSD 0x8(%RDI),%XMM8 |
0x4061eb MOV (%RDI),%R15 |
0x4061ee VMOVSD %XMM10,-0x50(%RBP) |
0x4061f3 VMOVSD %XMM9,-0x48(%RBP) |
0x4061f8 VMOVSD %XMM5,-0x38(%RBP) |
0x4061fd MOV 0x18(%R15),%R13 |
0x406201 VMOVSD %XMM8,-0x40(%RBP) |
0x406206 MOV %EAX,-0x68(%RBP) |
0x406209 CALL 403060 <omp_get_num_threads@plt> |
0x40620e MOV %EAX,%EBX |
0x406210 CALL 403150 <omp_get_thread_num@plt> |
0x406215 VMOVSD -0x40(%RBP),%XMM0 |
0x40621a VMOVSD -0x48(%RBP),%XMM9 |
0x40621f MOV %EAX,%ECX |
0x406221 MOV 0xc(%R13),%EAX |
0x406225 VMOVSD -0x50(%RBP),%XMM10 |
0x40622a CLTD |
0x40622b IDIV %EBX |
0x40622d CMP %EDX,%ECX |
0x40622f JL 406619 |
0x406235 IMUL %EAX,%ECX |
0x406238 ADD %ECX,%EDX |
0x40623a ADD %EDX,%EAX |
0x40623c MOV %EAX,-0x6c(%RBP) |
0x40623f CMP %EAX,%EDX |
0x406241 JGE 40662f |
0x406247 MOVSXD -0x68(%RBP),%RSI |
0x40624b MOVSXD %EDX,%RAX |
0x40624e MOV 0x78(%R13),%R14 |
0x406252 SAL $0x6,%EDX |
0x406255 VMULSD 0xc9c3(%RIP),%XMM0,%XMM8 |
0x40625d MOV %EDX,%ECX |
0x40625f VXORPD %XMM5,%XMM5,%XMM5 |
0x406263 VMOVSD 0xc985(%RIP),%XMM7 |
0x40626b LEA (,%RSI,4),%RDI |
0x406273 VMOVSD 0xc9ad(%RIP),%XMM6 |
0x40627b VMOVSD 0xc9ad(%RIP),%XMM11 |
0x406283 MOV %RDI,-0x78(%RBP) |
(21) 0x406287 MOV -0x68(%RBP),%R9D |
(21) 0x40628b MOV (%R14,%RAX,4),%R8D |
(21) 0x40628f TEST %R9D,%R9D |
(21) 0x406292 JLE 4065cf |
(21) 0x406298 MOV 0x80(%R13),%R11 |
(21) 0x40629f MOV %EAX,%ESI |
(21) 0x4062a1 MOV -0x78(%RBP),%RBX |
(21) 0x4062a5 MOV %ECX,-0x70(%RBP) |
(21) 0x4062a8 SAL $0x6,%ESI |
(21) 0x4062ab LEA (%R8,%RCX,1),%R10D |
(21) 0x4062af MOV %R13,-0x80(%RBP) |
(21) 0x4062b3 VMOVSD 0xc97d(%RIP),%XMM12 |
(21) 0x4062bb MOV (%R11,%RAX,8),%RDX |
(21) 0x4062bf MOVSXD %ESI,%R9 |
(21) 0x4062c2 MOV %R10D,-0x50(%RBP) |
(21) 0x4062c6 LEA -0x1(%R10),%R10D |
(21) 0x4062ca LEA (,%R9,8),%RDI |
(21) 0x4062d2 SUB %ESI,%R10D |
(21) 0x4062d5 MOV %R14,-0x48(%RBP) |
(21) 0x4062d9 LEA (%RDX,%RBX,1),%R8 |
(21) 0x4062dd MOV %RDI,-0x58(%RBP) |
(21) 0x4062e1 LEA 0x1(%R9,%R10,1),%RBX |
(21) 0x4062e6 MOV %R12,%R9 |
(21) 0x4062e9 MOV %R8,-0x60(%RBP) |
(21) 0x4062ed SAL $0x3,%RBX |
(21) 0x4062f1 MOV %RAX,-0x88(%RBP) |
(21) 0x4062f8 MOV %ESI,-0x64(%RBP) |
(23) 0x4062fb MOV (%RDX),%R11D |
(23) 0x4062fe TEST %R11D,%R11D |
(23) 0x406301 JS 406635 |
(23) 0x406307 MOV -0x48(%RBP),%R13 |
(23) 0x40630b MOVSXD %R11D,%R12 |
(23) 0x40630e MOV -0x64(%RBP),%EAX |
(23) 0x406311 MOV (%R13,%R12,4),%R14D |
(23) 0x406316 CMP %EAX,-0x50(%RBP) |
(23) 0x406319 JLE 4065a9 |
(23) 0x40631f LEA (%R12,%R12,2),%R12 |
(23) 0x406323 MOV %RDX,-0x40(%RBP) |
(23) 0x406327 SAL $0x6,%R11D |
(23) 0x40632b LEA (%R14,%R14,2),%RCX |
(23) 0x40632f SAL $0x9,%R12 |
(23) 0x406333 MOV -0x58(%RBP),%R8 |
(23) 0x406337 LEA (%R14,%R11,1),%R13D |
(23) 0x40633b VXORPD %XMM4,%XMM4,%XMM4 |
(23) 0x40633f LEA (%R12,%RCX,8),%R14 |
(23) 0x406343 NOPL (%RAX,%RAX,1) |
(24) 0x406348 CMP %R13D,%R11D |
(24) 0x40634b JGE 406598 |
(24) 0x406351 MOV 0x20(%R15),%RDI |
(24) 0x406355 LEA (%R8,%R8,2),%R10 |
(24) 0x406359 MOV 0x18(%RDI),%RCX |
(24) 0x40635d LEA (%RCX,%R12,1),%RAX |
(24) 0x406361 LEA (%RCX,%R10,1),%RDX |
(24) 0x406365 ADD %R14,%RCX |
(24) 0x406368 MOV %RCX,%RSI |
(24) 0x40636b SUB %RAX,%RSI |
(24) 0x40636e AND $0x8,%ESI |
(24) 0x406371 JE 406430 |
(24) 0x406377 VMOVSD 0x8(%RDX),%XMM2 |
(24) 0x40637c VSUBSD 0x8(%RAX),%XMM2,%XMM0 |
(24) 0x406381 VMOVSD (%RDX),%XMM1 |
(24) 0x406385 VSUBSD (%RAX),%XMM1,%XMM1 |
(24) 0x406389 VMOVSD 0x10(%RDX),%XMM13 |
(24) 0x40638e VSUBSD 0x10(%RAX),%XMM13,%XMM2 |
(24) 0x406393 VMULSD %XMM0,%XMM0,%XMM3 |
(24) 0x406397 VFMADD231SD %XMM1,%XMM1,%XMM3 |
(24) 0x40639c VFMADD231SD %XMM2,%XMM2,%XMM3 |
(24) 0x4063a1 VCOMISD %XMM3,%XMM9 |
(24) 0x4063a5 JB 406421 |
(24) 0x4063a7 VCOMISD %XMM4,%XMM3 |
(24) 0x4063ab JBE 406421 |
(24) 0x4063ad VDIVSD %XMM3,%XMM7,%XMM15 |
(24) 0x4063b1 MOV 0x30(%RDI),%RSI |
(24) 0x4063b5 ADD %R8,%RSI |
(24) 0x4063b8 VMULSD %XMM15,%XMM15,%XMM13 |
(24) 0x4063bd VMULSD %XMM15,%XMM10,%XMM3 |
(24) 0x4063c2 VMULSD %XMM8,%XMM15,%XMM14 |
(24) 0x4063c7 VMULSD %XMM3,%XMM13,%XMM3 |
(24) 0x4063cb VSUBSD %XMM7,%XMM3,%XMM13 |
(24) 0x4063cf VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(24) 0x4063d5 VMOVSD %XMM13,%XMM13,%XMM15 |
(24) 0x4063da VFMADD231SD %XMM6,%XMM13,%XMM5 |
(24) 0x4063df VMOVSD %XMM3,%XMM3,%XMM13 |
(24) 0x4063e3 VFMADD132SD %XMM11,%XMM12,%XMM13 |
(24) 0x4063e8 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(24) 0x4063ed VMULSD %XMM13,%XMM3,%XMM3 |
(24) 0x4063f2 VMOVSD %XMM15,(%RSI) |
(24) 0x4063f6 MOV 0x28(%RDI),%RSI |
(24) 0x4063fa ADD %R10,%RSI |
(24) 0x4063fd VMULSD %XMM14,%XMM3,%XMM14 |
(24) 0x406402 VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(24) 0x406407 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(24) 0x40640d VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(24) 0x406413 VMOVSD %XMM1,(%RSI) |
(24) 0x406417 VMOVSD %XMM0,0x8(%RSI) |
(24) 0x40641c VMOVSD %XMM14,0x10(%RSI) |
(24) 0x406421 ADD $0x18,%RAX |
(24) 0x406425 CMP %RAX,%RCX |
(24) 0x406428 JE 406598 |
(24) 0x40642e XCHG %AX,%AX |
(25) 0x406430 VMOVSD 0x8(%RDX),%XMM0 |
(25) 0x406435 VSUBSD 0x8(%RAX),%XMM0,%XMM0 |
(25) 0x40643a VMOVSD (%RDX),%XMM1 |
(25) 0x40643e VSUBSD (%RAX),%XMM1,%XMM1 |
(25) 0x406442 VMOVSD 0x10(%RDX),%XMM2 |
(25) 0x406447 VSUBSD 0x10(%RAX),%XMM2,%XMM2 |
(25) 0x40644c VMULSD %XMM0,%XMM0,%XMM15 |
(25) 0x406450 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(25) 0x406455 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(25) 0x40645a VCOMISD %XMM15,%XMM9 |
(25) 0x40645f JB 4064db |
(25) 0x406461 VCOMISD %XMM4,%XMM15 |
(25) 0x406465 JBE 4064db |
(25) 0x406467 VDIVSD %XMM15,%XMM7,%XMM3 |
(25) 0x40646c MOV 0x30(%RDI),%RSI |
(25) 0x406470 ADD %R8,%RSI |
(25) 0x406473 VMULSD %XMM3,%XMM3,%XMM13 |
(25) 0x406477 VMULSD %XMM3,%XMM10,%XMM15 |
(25) 0x40647b VMULSD %XMM8,%XMM3,%XMM14 |
(25) 0x406480 VMULSD %XMM15,%XMM13,%XMM3 |
(25) 0x406485 VSUBSD %XMM7,%XMM3,%XMM13 |
(25) 0x406489 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(25) 0x40648f VMOVSD %XMM13,%XMM13,%XMM15 |
(25) 0x406494 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(25) 0x406499 VMOVSD %XMM3,%XMM3,%XMM13 |
(25) 0x40649d VFMADD132SD %XMM11,%XMM12,%XMM13 |
(25) 0x4064a2 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(25) 0x4064a7 VMULSD %XMM13,%XMM3,%XMM3 |
(25) 0x4064ac VMOVSD %XMM15,(%RSI) |
(25) 0x4064b0 MOV 0x28(%RDI),%RSI |
(25) 0x4064b4 ADD %R10,%RSI |
(25) 0x4064b7 VMULSD %XMM14,%XMM3,%XMM14 |
(25) 0x4064bc VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(25) 0x4064c1 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(25) 0x4064c7 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(25) 0x4064cd VMOVSD %XMM1,(%RSI) |
(25) 0x4064d1 VMOVSD %XMM0,0x8(%RSI) |
(25) 0x4064d6 VMOVSD %XMM14,0x10(%RSI) |
(25) 0x4064db VMOVSD 0x8(%RDX),%XMM0 |
(25) 0x4064e0 VSUBSD 0x20(%RAX),%XMM0,%XMM0 |
(25) 0x4064e5 LEA 0x18(%RAX),%RSI |
(25) 0x4064e9 VMOVSD (%RDX),%XMM1 |
(25) 0x4064ed VSUBSD 0x18(%RAX),%XMM1,%XMM1 |
(25) 0x4064f2 VMOVSD 0x10(%RDX),%XMM2 |
(25) 0x4064f7 VSUBSD 0x28(%RAX),%XMM2,%XMM2 |
(25) 0x4064fc VMULSD %XMM0,%XMM0,%XMM15 |
(25) 0x406500 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(25) 0x406505 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(25) 0x40650a VCOMISD %XMM15,%XMM9 |
(25) 0x40650f JB 40658b |
(25) 0x406511 VCOMISD %XMM4,%XMM15 |
(25) 0x406515 JBE 40658b |
(25) 0x406517 VDIVSD %XMM15,%XMM7,%XMM3 |
(25) 0x40651c MOV 0x30(%RDI),%RAX |
(25) 0x406520 ADD %R8,%RAX |
(25) 0x406523 VMULSD %XMM3,%XMM3,%XMM13 |
(25) 0x406527 VMULSD %XMM3,%XMM10,%XMM15 |
(25) 0x40652b VMULSD %XMM8,%XMM3,%XMM14 |
(25) 0x406530 VMULSD %XMM15,%XMM13,%XMM3 |
(25) 0x406535 VSUBSD %XMM7,%XMM3,%XMM13 |
(25) 0x406539 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(25) 0x40653f VMOVSD %XMM13,%XMM13,%XMM15 |
(25) 0x406544 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(25) 0x406549 VMOVSD %XMM3,%XMM3,%XMM13 |
(25) 0x40654d VFMADD132SD %XMM11,%XMM12,%XMM13 |
(25) 0x406552 VFMADD213SD (%RAX),%XMM6,%XMM15 |
(25) 0x406557 VMULSD %XMM13,%XMM3,%XMM3 |
(25) 0x40655c VMOVSD %XMM15,(%RAX) |
(25) 0x406560 MOV 0x28(%RDI),%RAX |
(25) 0x406564 ADD %R10,%RAX |
(25) 0x406567 VMULSD %XMM14,%XMM3,%XMM14 |
(25) 0x40656c VFNMADD213SD (%RAX),%XMM14,%XMM1 |
(25) 0x406571 VFNMADD213SD 0x8(%RAX),%XMM14,%XMM0 |
(25) 0x406577 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(25) 0x40657d VMOVSD %XMM1,(%RAX) |
(25) 0x406581 VMOVSD %XMM0,0x8(%RAX) |
(25) 0x406586 VMOVSD %XMM14,0x10(%RAX) |
(25) 0x40658b LEA 0x18(%RSI),%RAX |
(25) 0x40658f CMP %RAX,%RCX |
(25) 0x406592 JNE 406430 |
(24) 0x406598 ADD $0x8,%R8 |
(24) 0x40659c CMP %R8,%RBX |
(24) 0x40659f JNE 406348 |
(23) 0x4065a5 MOV -0x40(%RBP),%RDX |
(23) 0x4065a9 MOV -0x60(%RBP),%R11 |
(23) 0x4065ad ADD $0x4,%RDX |
(23) 0x4065b1 CMP %R11,%RDX |
(23) 0x4065b4 JNE 4062fb |
(21) 0x4065ba MOV -0x80(%RBP),%R13 |
(21) 0x4065be MOV -0x48(%RBP),%R14 |
(21) 0x4065c2 MOV %R9,%R12 |
(21) 0x4065c5 MOV -0x88(%RBP),%RAX |
(21) 0x4065cc MOV -0x70(%RBP),%ECX |
(21) 0x4065cf INC %RAX |
(21) 0x4065d2 ADD $0x40,%ECX |
(21) 0x4065d5 CMP %EAX,-0x6c(%RBP) |
(21) 0x4065d8 JG 406287 |
0x4065de MOV 0x28(%R12),%R8 |
0x4065e3 LEA 0x28(%R12),%R15 |
(22) 0x4065e8 VMOVQ %R8,%XMM9 |
(22) 0x4065ed MOV %R8,%RAX |
(22) 0x4065f0 VADDSD %XMM9,%XMM5,%XMM10 |
(22) 0x4065f5 VMOVQ %XMM10,%RBX |
(22) 0x4065fa LOCK CMPXCHG %RBX,(%R15) |
(22) 0x4065ff MOV %R8,%R9 |
(22) 0x406602 MOV %RAX,%R8 |
(22) 0x406605 CMP %RAX,%R9 |
(22) 0x406608 JNE 4065e8 |
0x40660a ADD $0x68,%RSP |
0x40660e POP %RBX |
0x40660f POP %R12 |
0x406611 POP %R13 |
0x406613 POP %R14 |
0x406615 POP %R15 |
0x406617 POP %RBP |
0x406618 RET |
0x406619 INC %EAX |
0x40661b XOR %EDX,%EDX |
0x40661d IMUL %EAX,%ECX |
0x406620 ADD %ECX,%EDX |
0x406622 ADD %EDX,%EAX |
0x406624 MOV %EAX,-0x6c(%RBP) |
0x406627 CMP %EAX,%EDX |
0x406629 JL 406247 |
0x40662f VXORPD %XMM5,%XMM5,%XMM5 |
0x406633 JMP 4065de |
0x406635 MOV $0x412a78,%ECX |
0x40663a MOV $0xb6,%EDX |
0x40663f MOV $0x411bd8,%ESI |
0x406644 MOV $0x411136,%EDI |
0x406649 CALL 4030b0 <__assert_fail@plt> |
0x40664e XCHG %AX,%AX |
Path / |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 83 |
loop length | 279 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.83 cycles |
front end | 13.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
cycles | 5.10 | 7.73 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.40 |
Stall cycles | 0.00 |
Front-end | 13.83 |
Dispatch | 8.50 |
DIV/SQRT | 6.00 |
Overall L1 | 13.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 7% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 10% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x18(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x20(%RDI),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM9,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM5,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM8,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 406619 <ljForce._omp_fn.1+0x459> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40662f <ljForce._omp_fn.1+0x46f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD -0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMULSD 0xc9c3(%RIP),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xc985(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RSI,4),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xc9ad(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xc9ad(%RIP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 406247 <ljForce._omp_fn.1+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4065de <ljForce._omp_fn.1+0x41e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x412a78,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x411bd8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x411136,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 83 |
loop length | 279 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.83 cycles |
front end | 13.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
cycles | 5.10 | 7.73 | 8.33 | 8.33 | 8.50 | 5.07 | 4.90 | 8.50 | 8.50 | 8.50 | 4.93 | 8.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.40 |
Stall cycles | 0.00 |
Front-end | 13.83 |
Dispatch | 8.50 |
DIV/SQRT | 6.00 |
Overall L1 | 13.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 7% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 10% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x18(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x20(%RDI),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM9,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM5,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM8,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 406619 <ljForce._omp_fn.1+0x459> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40662f <ljForce._omp_fn.1+0x46f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD -0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMULSD 0xc9c3(%RIP),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xc985(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RSI,4),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xc9ad(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xc9ad(%RIP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x68,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 406247 <ljForce._omp_fn.1+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4065de <ljForce._omp_fn.1+0x41e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x412a78,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x411bd8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x411136,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030b0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼ljForce._omp_fn.1– | 61.38 | 9.52 |
▼Loop 21 - ljForce.c:175-216 - exec– | 0.02 | 0 |
▼Loop 23 - ljForce.c:178-216 - exec– | 0.27 | 0.03 |
▼Loop 24 - ljForce.c:187-216 - exec– | 4.74 | 0.55 |
○Loop 25 - ljForce.c:191-216 - exec | 56.34 | 6.56 |
○Loop 22 - ljForce.c:172-172 - exec | 0 | 0 |