Function: kineticEnergy._omp_fn.0 | Module: exec | Source: timestep.c:107-116 | Coverage: 0.36% |
---|
Function: kineticEnergy._omp_fn.0 | Module: exec | Source: timestep.c:107-116 | Coverage: 0.36% |
---|
/scratch_na/users/xoserete/qaas_runs/171-416-1926/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116 |
-------------------------------------------------------------------------------- |
107: #pragma omp parallel for reduction(+:kenergy) |
108: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
109: { |
110: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
111: { |
112: int iSpecies = s->atoms->iSpecies[iOff]; |
113: real_t invMass = 0.5/s->species[iSpecies].mass; |
114: kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] + |
115: s->atoms->p[iOff][1] * s->atoms->p[iOff][1] + |
116: s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass; |
0x40ef70 PUSH %RBP |
0x40ef71 MOV %RSP,%RBP |
0x40ef74 PUSH %R14 |
0x40ef76 PUSH %R13 |
0x40ef78 PUSH %R12 |
0x40ef7a MOV %RDI,%R12 |
0x40ef7d PUSH %RBX |
0x40ef7e MOV (%RDI),%RBX |
0x40ef81 MOV 0x18(%RBX),%R14 |
0x40ef85 CALL 403070 <omp_get_num_threads@plt> |
0x40ef8a MOV %EAX,%R13D |
0x40ef8d CALL 403160 <omp_get_thread_num@plt> |
0x40ef92 MOV %EAX,%R8D |
0x40ef95 MOV 0xc(%R14),%EAX |
0x40ef99 CLTD |
0x40ef9a IDIV %R13D |
0x40ef9d CMP %EDX,%R8D |
0x40efa0 JL 40f200 |
0x40efa6 IMUL %EAX,%R8D |
0x40efaa VXORPD %XMM0,%XMM0,%XMM0 |
0x40efae ADD %EDX,%R8D |
0x40efb1 ADD %R8D,%EAX |
0x40efb4 CMP %EAX,%R8D |
0x40efb7 JGE 40f1d8 |
0x40efbd MOVSXD %R8D,%R9 |
0x40efc0 MOV 0x78(%R14),%R13 |
0x40efc4 VMOVSD 0x1b0c(%RIP),%XMM2 |
0x40efcc SAL $0x6,%R8D |
0x40efd0 LEA (%R9,%R9,2),%R11 |
0x40efd4 SAL $0x9,%R11 |
0x40efd8 NOPL (%RAX,%RAX,1) |
(96) 0x40efe0 MOVSXD (%R13,%R9,4),%RSI |
(96) 0x40efe5 TEST %ESI,%ESI |
(96) 0x40efe7 JLE 40f1c1 |
(96) 0x40efed MOV 0x20(%RBX),%R14 |
(96) 0x40eff1 MOVSXD %R8D,%RCX |
(96) 0x40eff4 MOV 0x28(%RBX),%RDI |
(96) 0x40eff8 MOV 0x10(%R14),%R10 |
(96) 0x40effc MOV 0x20(%R14),%RDX |
(96) 0x40f000 MOV %R9,%R14 |
(96) 0x40f003 SAL $0x6,%R14 |
(96) 0x40f007 ADD %R14,%RSI |
(96) 0x40f00a LEA (%R10,%RCX,4),%RCX |
(96) 0x40f00e ADD %R11,%RDX |
(96) 0x40f011 LEA (%R10,%RSI,4),%R10 |
(96) 0x40f015 MOV %R10,%RSI |
(96) 0x40f018 SUB %RCX,%RSI |
(96) 0x40f01b SUB $0x4,%RSI |
(96) 0x40f01f SHR $0x2,%RSI |
(96) 0x40f023 INC %RSI |
(96) 0x40f026 AND $0x3,%ESI |
(96) 0x40f029 JE 40f0ed |
(96) 0x40f02f CMP $0x1,%RSI |
(96) 0x40f033 JE 40f0ab |
(96) 0x40f035 CMP $0x2,%RSI |
(96) 0x40f039 JE 40f073 |
(96) 0x40f03b VMOVSD 0x8(%RDX),%XMM3 |
(96) 0x40f040 MOVSXD (%RCX),%R14 |
(96) 0x40f043 ADD $0x18,%RDX |
(96) 0x40f047 ADD $0x4,%RCX |
(96) 0x40f04b VMOVSD -0x18(%RDX),%XMM1 |
(96) 0x40f050 VMOVSD -0x8(%RDX),%XMM5 |
(96) 0x40f055 VMULSD %XMM3,%XMM3,%XMM4 |
(96) 0x40f059 SAL $0x4,%R14 |
(96) 0x40f05d VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM6 |
(96) 0x40f064 VFMADD231SD %XMM1,%XMM1,%XMM4 |
(96) 0x40f069 VFMADD132SD %XMM5,%XMM4,%XMM5 |
(96) 0x40f06e VFMADD231SD %XMM5,%XMM6,%XMM0 |
(96) 0x40f073 VMOVSD 0x8(%RDX),%XMM8 |
(96) 0x40f078 MOVSXD (%RCX),%RSI |
(96) 0x40f07b ADD $0x18,%RDX |
(96) 0x40f07f ADD $0x4,%RCX |
(96) 0x40f083 VMOVSD -0x18(%RDX),%XMM7 |
(96) 0x40f088 VMOVSD -0x8(%RDX),%XMM10 |
(96) 0x40f08d VMULSD %XMM8,%XMM8,%XMM9 |
(96) 0x40f092 SAL $0x4,%RSI |
(96) 0x40f096 VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM11 |
(96) 0x40f09c VFMADD231SD %XMM7,%XMM7,%XMM9 |
(96) 0x40f0a1 VFMADD132SD %XMM10,%XMM9,%XMM10 |
(96) 0x40f0a6 VFMADD231SD %XMM10,%XMM11,%XMM0 |
(96) 0x40f0ab VMOVSD 0x8(%RDX),%XMM13 |
(96) 0x40f0b0 MOVSXD (%RCX),%R14 |
(96) 0x40f0b3 ADD $0x4,%RCX |
(96) 0x40f0b7 ADD $0x18,%RDX |
(96) 0x40f0bb VMOVSD -0x18(%RDX),%XMM12 |
(96) 0x40f0c0 VMOVSD -0x8(%RDX),%XMM15 |
(96) 0x40f0c5 VMULSD %XMM13,%XMM13,%XMM14 |
(96) 0x40f0ca SAL $0x4,%R14 |
(96) 0x40f0ce VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM1 |
(96) 0x40f0d5 VFMADD231SD %XMM12,%XMM12,%XMM14 |
(96) 0x40f0da VFMADD132SD %XMM15,%XMM14,%XMM15 |
(96) 0x40f0df VFMADD231SD %XMM15,%XMM1,%XMM0 |
(96) 0x40f0e4 CMP %RCX,%R10 |
(96) 0x40f0e7 JE 40f1c1 |
(97) 0x40f0ed VMOVSD 0x8(%RDX),%XMM3 |
(97) 0x40f0f2 MOVSXD (%RCX),%RSI |
(97) 0x40f0f5 ADD $0x10,%RCX |
(97) 0x40f0f9 ADD $0x60,%RDX |
(97) 0x40f0fd VMOVSD -0x60(%RDX),%XMM4 |
(97) 0x40f102 VMOVSD -0x50(%RDX),%XMM6 |
(97) 0x40f107 VMULSD %XMM3,%XMM3,%XMM5 |
(97) 0x40f10b VMOVSD -0x40(%RDX),%XMM8 |
(97) 0x40f110 SAL $0x4,%RSI |
(97) 0x40f114 VMOVSD -0x28(%RDX),%XMM13 |
(97) 0x40f119 VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM7 |
(97) 0x40f11f VMOVSD -0x38(%RDX),%XMM10 |
(97) 0x40f124 VMOVSD -0x30(%RDX),%XMM12 |
(97) 0x40f129 VMULSD %XMM8,%XMM8,%XMM9 |
(97) 0x40f12e VMOVSD -0x10(%RDX),%XMM1 |
(97) 0x40f133 MOVSXD -0xc(%RCX),%R14 |
(97) 0x40f137 VMULSD %XMM13,%XMM13,%XMM14 |
(97) 0x40f13c VMOVSD -0x20(%RDX),%XMM15 |
(97) 0x40f141 VMOVSD -0x18(%RDX),%XMM3 |
(97) 0x40f146 SAL $0x4,%R14 |
(97) 0x40f14a MOVSXD -0x8(%RCX),%RSI |
(97) 0x40f14e VFMADD231SD %XMM4,%XMM4,%XMM5 |
(97) 0x40f153 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM11 |
(97) 0x40f15a MOVSXD -0x4(%RCX),%R14 |
(97) 0x40f15e SAL $0x4,%RSI |
(97) 0x40f162 VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM4 |
(97) 0x40f168 SAL $0x4,%R14 |
(97) 0x40f16c VFMADD231SD %XMM12,%XMM12,%XMM14 |
(97) 0x40f171 VFMADD132SD %XMM6,%XMM5,%XMM6 |
(97) 0x40f176 VMULSD %XMM1,%XMM1,%XMM5 |
(97) 0x40f17a VFMADD132SD %XMM15,%XMM14,%XMM15 |
(97) 0x40f17f VFMADD132SD %XMM6,%XMM0,%XMM7 |
(97) 0x40f184 VMOVSD -0x48(%RDX),%XMM0 |
(97) 0x40f189 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM6 |
(97) 0x40f190 VFMADD231SD %XMM3,%XMM3,%XMM5 |
(97) 0x40f195 VFMADD231SD %XMM0,%XMM0,%XMM9 |
(97) 0x40f19a VMOVSD -0x8(%RDX),%XMM0 |
(97) 0x40f19f VFMADD132SD %XMM0,%XMM5,%XMM0 |
(97) 0x40f1a4 VFMADD132SD %XMM10,%XMM9,%XMM10 |
(97) 0x40f1a9 VFMADD132SD %XMM10,%XMM7,%XMM11 |
(97) 0x40f1ae VFMADD132SD %XMM15,%XMM11,%XMM4 |
(97) 0x40f1b3 VFMADD132SD %XMM6,%XMM4,%XMM0 |
(97) 0x40f1b8 CMP %RCX,%R10 |
(97) 0x40f1bb JNE 40f0ed |
(96) 0x40f1c1 INC %R9 |
(96) 0x40f1c4 ADD $0x40,%R8D |
(96) 0x40f1c8 ADD $0x600,%R11 |
(96) 0x40f1cf CMP %R9D,%EAX |
(96) 0x40f1d2 JG 40efe0 |
0x40f1d8 MOV 0x8(%R12),%RAX |
0x40f1dd LEA 0x8(%R12),%RBX |
(95) 0x40f1e2 VMOVQ %RAX,%XMM2 |
(95) 0x40f1e7 VADDSD %XMM2,%XMM0,%XMM7 |
(95) 0x40f1eb VMOVQ %XMM7,%R12 |
(95) 0x40f1f0 LOCK CMPXCHG %R12,(%RBX) |
(95) 0x40f1f5 JNE 40f1e2 |
0x40f1f7 POP %RBX |
0x40f1f8 POP %R12 |
0x40f1fa POP %R13 |
0x40f1fc POP %R14 |
0x40f1fe POP %RBP |
0x40f1ff RET |
0x40f200 INC %EAX |
0x40f202 XOR %EDX,%EDX |
0x40f204 JMP 40efa6 |
0x40f209 NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○97.67 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○2.33 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | timestep.c:107-116 |
Module | exec |
nb instructions | 43 |
nb uops | 48 |
loop length | 147 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 8.00 cycles |
front end | 8.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
cycles | 3.00 | 5.33 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.71 |
Stall cycles | 0.00 |
Front-end | 8.00 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 8.00 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 6% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 9% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40f200 <kineticEnergy._omp_fn.0+0x290> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40f1d8 <kineticEnergy._omp_fn.0+0x268> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R14),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1b0c(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%R8D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x9,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%R12),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40efa6 <kineticEnergy._omp_fn.0+0x36> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:107-116 |
Module | exec |
nb instructions | 43 |
nb uops | 48 |
loop length | 147 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 8.00 cycles |
front end | 8.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
cycles | 3.00 | 5.33 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.71 |
Stall cycles | 0.00 |
Front-end | 8.00 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 8.00 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 50% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 6% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 18% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 9% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40f200 <kineticEnergy._omp_fn.0+0x290> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40f1d8 <kineticEnergy._omp_fn.0+0x268> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R14),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1b0c(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%R8D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x9,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%R12),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40efa6 <kineticEnergy._omp_fn.0+0x36> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼kineticEnergy._omp_fn.0– | 0.36 | 0.06 |
▼Loop 96 - timestep.c:110-116 - exec– | 0.12 | 0.01 |
○Loop 97 - timestep.c:110-116 - exec | 0.23 | 0.02 |
○Loop 95 - timestep.c:107-107 - exec | 0 | 0 |