Loop Id: 261 | Module: exec | Source: field_summary_kernel.f90:62-71 | Coverage: 0.29% |
---|
Loop Id: 261 | Module: exec | Source: field_summary_kernel.f90:62-71 | Coverage: 0.29% |
---|
0x437880 VMOVUPD (%R11,%RAX,8),%XMM10 [13] |
0x437886 VMOVUPD (%RBX,%RAX,8),%XMM15 [8] |
0x43788b LEA 0x1(%RAX),%RDX |
0x43788f VMULPD %XMM10,%XMM10,%XMM0 |
0x437894 VMOVUPD (%R9,%RAX,8),%XMM10 [14] |
0x43789a VFMADD132PD %XMM15,%XMM0,%XMM15 |
0x43789f VMOVUPD (%R10,%RAX,8),%XMM0 [5] |
0x4378a5 VMULPD %XMM3,%XMM15,%XMM11 |
0x4378a9 VUNPCKHPD %XMM11,%XMM11,%XMM1 |
0x4378ae VADDPD %XMM11,%XMM1,%XMM15 |
0x4378b3 VMULPD %XMM10,%XMM10,%XMM11 |
0x4378b8 VFMADD132PD %XMM0,%XMM11,%XMM0 |
0x4378bd VMULPD %XMM3,%XMM0,%XMM1 |
0x4378c1 VUNPCKHPD %XMM1,%XMM1,%XMM0 |
0x4378c5 VADDPD %XMM1,%XMM0,%XMM10 |
0x4378c9 VADDSD %XMM10,%XMM15,%XMM15 |
0x4378ce VMOVSD (%R8,%RAX,8),%XMM10 [7] |
0x4378d4 VMULSD %XMM4,%XMM15,%XMM1 |
0x4378d8 VMULSD (%RDI,%RAX,8),%XMM10,%XMM11 [1] |
0x4378dd VFMADD231SD (%RSI,%RAX,8),%XMM11,%XMM12 [9] |
0x4378e3 VADDSD %XMM11,%XMM13,%XMM13 |
0x4378e8 VFMADD132SD %XMM1,%XMM2,%XMM11 |
0x4378ed VMOVUPD (%R11,%RDX,8),%XMM2 [11] |
0x4378f3 VADDSD %XMM10,%XMM14,%XMM14 |
0x4378f8 VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM10 [4] |
0x4378fe VMOVUPD (%RBX,%RDX,8),%XMM9 [10] |
0x437903 ADD $0x2,%RAX |
0x437907 VMULPD %XMM2,%XMM2,%XMM0 |
0x43790b VMOVUPD (%R9,%RDX,8),%XMM2 [15] |
0x437911 VFMADD132PD %XMM9,%XMM0,%XMM9 |
0x437916 VMOVUPD (%R10,%RDX,8),%XMM0 [2] |
0x43791c VMULPD %XMM3,%XMM9,%XMM15 |
0x437920 VUNPCKHPD %XMM15,%XMM15,%XMM1 |
0x437925 VADDPD %XMM15,%XMM1,%XMM9 |
0x43792a VMULPD %XMM2,%XMM2,%XMM15 |
0x43792e VFMADD132PD %XMM0,%XMM15,%XMM0 |
0x437933 VMULPD %XMM3,%XMM0,%XMM1 |
0x437937 VUNPCKHPD %XMM1,%XMM1,%XMM0 |
0x43793b VADDPD %XMM1,%XMM0,%XMM2 |
0x43793f VADDSD %XMM2,%XMM9,%XMM15 |
0x437943 VMOVSD (%R8,%RDX,8),%XMM9 [16] |
0x437949 VMULSD %XMM4,%XMM15,%XMM1 |
0x43794d VMULSD (%RDI,%RDX,8),%XMM9,%XMM2 [6] |
0x437952 VADDSD %XMM9,%XMM14,%XMM14 |
0x437957 VADDSD %XMM2,%XMM13,%XMM13 |
0x43795b VFMADD231SD (%RSI,%RDX,8),%XMM2,%XMM12 [12] |
0x437961 VFMADD132SD (%RCX,%RDX,8),%XMM10,%XMM9 [3] |
0x437967 VFMADD132SD %XMM1,%XMM11,%XMM2 |
0x43796c CMP %EAX,%R12D |
0x43796f JGE 437880 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71 |
-------------------------------------------------------------------------------- |
62: vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2) |
63: ENDDO |
64: ENDDO |
65: cell_vol=volume(j,k) |
66: cell_mass=cell_vol*density0(j,k) |
67: vol=vol+cell_vol |
68: mass=mass+cell_mass |
69: ie=ie+cell_mass*energy0(j,k) |
70: ke=ke+cell_mass*0.5*vsqrd |
71: press=press+cell_vol*pressure(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.06 |
CQA speedup if fully vectorized | 2.59 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | P8, P9, |
Function | __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0.lto_priv.0 |
Source | field_summary_kernel.f90:62-71 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 11.00 |
CQA cycles if no scalar integer | 11.00 |
CQA cycles if FP arith vectorized | 5.33 |
CQA cycles if fully vectorized | 4.25 |
Front-end cycles | 8.17 |
DIV/SQRT cycles | 0.75 |
P0 cycles | 0.75 |
P1 cycles | 0.50 |
P2 cycles | 0.50 |
P3 cycles | 0.50 |
P4 cycles | 5.33 |
P5 cycles | 5.33 |
P6 cycles | 5.33 |
P7 cycles | 11.00 |
P8 cycles | 11.00 |
P9 cycles | 7.00 |
P10 cycles | 7.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 8 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 50.00 |
Nb uops | 49.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 5.64 |
Nb FLOP add-sub | 14.00 |
Nb FLOP mul | 20.00 |
Nb FLOP fma | 14.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.45 |
Bytes prefetched | 0.00 |
Bytes loaded | 192.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 8.00 |
Stride n | 8.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 52.17 |
Vectorization ratio load | 50.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 66.67 |
Vectorization ratio add_sub | 40.00 |
Vectorization ratio fma | 40.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 19.02 |
Vector-efficiency ratio load | 18.75 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 20.83 |
Vector-efficiency ratio add_sub | 17.50 |
Vector-efficiency ratio fma | 17.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.06 |
CQA speedup if fully vectorized | 2.59 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | P8, P9, |
Function | __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0.lto_priv.0 |
Source | field_summary_kernel.f90:62-71 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 11.00 |
CQA cycles if no scalar integer | 11.00 |
CQA cycles if FP arith vectorized | 5.33 |
CQA cycles if fully vectorized | 4.25 |
Front-end cycles | 8.17 |
DIV/SQRT cycles | 0.75 |
P0 cycles | 0.75 |
P1 cycles | 0.50 |
P2 cycles | 0.50 |
P3 cycles | 0.50 |
P4 cycles | 5.33 |
P5 cycles | 5.33 |
P6 cycles | 5.33 |
P7 cycles | 11.00 |
P8 cycles | 11.00 |
P9 cycles | 7.00 |
P10 cycles | 7.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 8 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 50.00 |
Nb uops | 49.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 5.64 |
Nb FLOP add-sub | 14.00 |
Nb FLOP mul | 20.00 |
Nb FLOP fma | 14.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.45 |
Bytes prefetched | 0.00 |
Bytes loaded | 192.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 8.00 |
Stride n | 8.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 52.17 |
Vectorization ratio load | 50.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 66.67 |
Vectorization ratio add_sub | 40.00 |
Vectorization ratio fma | 40.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 19.02 |
Vector-efficiency ratio load | 18.75 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 20.83 |
Vector-efficiency ratio add_sub | 17.50 |
Vector-efficiency ratio fma | 17.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0.lto_priv.0 |
Source file and lines | field_summary_kernel.f90:62-71 |
Module | exec |
nb instructions | 50 |
nb uops | 49 |
loop length | 245 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 12 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.83 |
micro-operation queue | 8.17 cycles |
front end | 8.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 5.33 | 5.33 | 5.33 | 11.00 | 11.00 | 7.00 | 7.00 | 0.00 | 0.00 |
cycles | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 5.33 | 5.33 | 5.33 | 11.00 | 11.00 | 7.00 | 7.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 8.00 |
Front-end | 8.17 |
Dispatch | 11.00 |
Data deps. | 8.00 |
Overall L1 | 11.00 |
all | 52% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 66% |
add-sub | 40% |
fma | 40% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 19% |
load | 18% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 20% |
add-sub | 17% |
fma | 17% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R11,%RAX,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD (%RBX,%RAX,8),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
LEA 0x1(%RAX),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMULPD %XMM10,%XMM10,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD (%R9,%RAX,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM15,%XMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%R10,%RAX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM3,%XMM15,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM11,%XMM11,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM11,%XMM1,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM10,%XMM10,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM0,%XMM11,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM3,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM1,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM1,%XMM0,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM10,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD (%R8,%RAX,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM4,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD (%RDI,%RAX,8),%XMM10,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD231SD (%RSI,%RAX,8),%XMM11,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM11,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD132SD %XMM1,%XMM2,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%R11,%RDX,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM10,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%RBX,%RDX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x2,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMULPD %XMM2,%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD (%R9,%RDX,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM9,%XMM0,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%R10,%RDX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM3,%XMM9,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM15,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM15,%XMM1,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM2,%XMM2,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM0,%XMM15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM3,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM1,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM2,%XMM9,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD (%R8,%RDX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM4,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD (%RDI,%RDX,8),%XMM9,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM9,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM2,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD231SD (%RSI,%RDX,8),%XMM2,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD (%RCX,%RDX,8),%XMM10,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD %XMM1,%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EAX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 437880 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0.lto_priv.0+0x2f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0.lto_priv.0 |
Source file and lines | field_summary_kernel.f90:62-71 |
Module | exec |
nb instructions | 50 |
nb uops | 49 |
loop length | 245 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 12 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.83 |
micro-operation queue | 8.17 cycles |
front end | 8.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 5.33 | 5.33 | 5.33 | 11.00 | 11.00 | 7.00 | 7.00 | 0.00 | 0.00 |
cycles | 0.75 | 0.75 | 0.50 | 0.50 | 0.50 | 5.33 | 5.33 | 5.33 | 11.00 | 11.00 | 7.00 | 7.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 8.00 |
Front-end | 8.17 |
Dispatch | 11.00 |
Data deps. | 8.00 |
Overall L1 | 11.00 |
all | 52% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 66% |
add-sub | 40% |
fma | 40% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 19% |
load | 18% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 20% |
add-sub | 17% |
fma | 17% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R11,%RAX,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD (%RBX,%RAX,8),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
LEA 0x1(%RAX),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMULPD %XMM10,%XMM10,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD (%R9,%RAX,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM15,%XMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%R10,%RAX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM3,%XMM15,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM11,%XMM11,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM11,%XMM1,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM10,%XMM10,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM0,%XMM11,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM3,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM1,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM1,%XMM0,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM10,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD (%R8,%RAX,8),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM4,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD (%RDI,%RAX,8),%XMM10,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD231SD (%RSI,%RAX,8),%XMM11,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM11,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD132SD %XMM1,%XMM2,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%R11,%RDX,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM10,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD132SD (%RCX,%RAX,8),%XMM9,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%RBX,%RDX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x2,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMULPD %XMM2,%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD (%R9,%RDX,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM9,%XMM0,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD (%R10,%RDX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM3,%XMM9,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM15,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM15,%XMM1,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %XMM2,%XMM2,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD132PD %XMM0,%XMM15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM3,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUNPCKHPD %XMM1,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VADDPD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM2,%XMM9,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD (%R8,%RDX,8),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM4,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD (%RDI,%RDX,8),%XMM9,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM9,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM2,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD231SD (%RSI,%RDX,8),%XMM2,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD (%RCX,%RDX,8),%XMM10,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD %XMM1,%XMM11,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EAX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 437880 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0.lto_priv.0+0x2f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |