Loop Id: 225 | Module: exec | Source: calc_dt_kernel.f90:93-129 | Coverage: 0.02% |
---|
Loop Id: 225 | Module: exec | Source: calc_dt_kernel.f90:93-129 | Coverage: 0.02% |
---|
0x433860 MOV -0x58(%RBP),%RDX |
0x433864 VMOVQ %XMM19,%RAX |
0x43386a VMOVSD (%R9),%XMM4 |
0x43386f VMOVSD (%RCX),%XMM9 |
0x433873 VADDSD (%R8),%XMM4,%XMM2 |
0x433878 VMOVSD (%RSI),%XMM8 |
0x43387c VMULSD (%RDI),%XMM2,%XMM4 |
0x433880 VMOVSD (%RAX,%RDX,8),%XMM18 |
0x433887 MOV -0x80(%RBP),%RAX |
0x43388b MOV -0x88(%RBP),%RDX |
0x433892 VMOVSD (%RAX),%XMM11 |
0x433896 VMOVSD (%RDX),%XMM17 |
0x43389c VMOVQ %XMM29,%RAX |
0x4338a2 VMOVQ %XMM28,%RDX |
0x4338a8 VMOVSD (%RAX),%XMM15 |
0x4338ac VMOVSD (%RDX),%XMM14 |
0x4338b0 VXORPD %XMM20,%XMM11,%XMM16 |
0x4338b6 XOR %EAX,%EAX |
0x4338b8 VADDSD %XMM15,%XMM15,%XMM15 |
0x4338bd VADDSD %XMM14,%XMM14,%XMM14 |
0x4338c2 JMP 4338f5 |
(226) 0x4338d0 MOV -0x48(%RBP),%RDX |
(226) 0x4338d4 VMOVSD (%RDX),%XMM3 |
(226) 0x4338d8 VMINSD %XMM7,%XMM3,%XMM7 |
(226) 0x4338dc LEA 0x1(%RAX),%RDX |
(226) 0x4338e0 VMINSD %XMM1,%XMM7,%XMM1 |
(226) 0x4338e4 VMINSD %XMM1,%XMM12,%XMM12 |
(226) 0x4338e8 CMP %RAX,-0x38(%RBP) |
(226) 0x4338ec JE 4339f0 |
(226) 0x4338f2 MOV %RDX,%RAX |
(226) 0x4338f5 VMOVSD (%R13,%RAX,8),%XMM3 |
(226) 0x4338fc VMOVSD (%R14,%RAX,8),%XMM2 |
(226) 0x433902 VADDSD %XMM3,%XMM3,%XMM5 |
(226) 0x433906 VDIVSD (%R12,%RAX,8),%XMM5,%XMM0 |
(226) 0x43390c VFMADD132SD %XMM2,%XMM0,%XMM2 |
(226) 0x433911 VMOVSD %XMM4,%XMM4,%XMM0 |
(226) 0x433915 VANDPD %XMM6,%XMM0,%XMM3 |
(226) 0x433919 VMOVSD (%RBX,%RAX,8),%XMM5 |
(226) 0x43391e VMOVSD 0x8(%R8,%RAX,8),%XMM7 |
(226) 0x433925 VMULSD %XMM5,%XMM11,%XMM10 |
(226) 0x433929 VADDSD 0x8(%R9,%RAX,8),%XMM7,%XMM1 |
(226) 0x433930 VMULSD 0x8(%RDI,%RAX,8),%XMM1,%XMM4 |
(226) 0x433936 VMAXSD %XMM10,%XMM3,%XMM1 |
(226) 0x43393b VANDPD %XMM6,%XMM4,%XMM3 |
(226) 0x43393f VMULSD %XMM5,%XMM15,%XMM7 |
(226) 0x433943 VMAXSD %XMM3,%XMM1,%XMM1 |
(226) 0x433947 VMOVSD %XMM8,%XMM8,%XMM3 |
(226) 0x43394b VDIVSD %XMM1,%XMM7,%XMM7 |
(226) 0x43394f VMOVSD 0x8(%RSI,%RAX,8),%XMM8 |
(226) 0x433955 VADDSD %XMM8,%XMM3,%XMM1 |
(226) 0x43395a VMULSD (%R11,%RAX,8),%XMM1,%XMM3 |
(226) 0x433960 VMOVSD %XMM9,%XMM9,%XMM1 |
(226) 0x433964 VSUBSD %XMM3,%XMM4,%XMM30 |
(226) 0x43396a VMOVSD 0x8(%RCX,%RAX,8),%XMM9 |
(226) 0x433970 VANDPD %XMM6,%XMM3,%XMM3 |
(226) 0x433974 VADDSD %XMM9,%XMM1,%XMM1 |
(226) 0x433979 VMULSD (%R10,%RAX,8),%XMM1,%XMM1 |
(226) 0x43397f VSUBSD %XMM0,%XMM1,%XMM0 |
(226) 0x433983 VANDPD %XMM6,%XMM1,%XMM1 |
(226) 0x433987 VADDSD %XMM30,%XMM0,%XMM0 |
(226) 0x43398d VSQRTSD %XMM2,%XMM2,%XMM2 |
(226) 0x433991 VMAXSD %XMM3,%XMM1,%XMM1 |
(226) 0x433995 VMULSD %XMM5,%XMM14,%XMM30 |
(226) 0x43399b VMAXSD %XMM10,%XMM1,%XMM10 |
(226) 0x4339a0 VMINSD (%R15,%RAX,8),%XMM18,%XMM3 |
(226) 0x4339a7 VDIVSD %XMM10,%XMM30,%XMM1 |
(226) 0x4339ad VMAXSD %XMM2,%XMM11,%XMM2 |
(226) 0x4339b1 VMULSD %XMM17,%XMM3,%XMM10 |
(226) 0x4339b7 VADDSD %XMM5,%XMM5,%XMM5 |
(226) 0x4339bb VDIVSD %XMM2,%XMM10,%XMM3 |
(226) 0x4339bf VDIVSD %XMM5,%XMM0,%XMM0 |
(226) 0x4339c3 VMINSD %XMM3,%XMM1,%XMM1 |
(226) 0x4339c7 VCOMISD %XMM0,%XMM16 |
(226) 0x4339cd JBE 4338d0 |
(226) 0x4339d3 VMOVQ %XMM22,%RDX |
(226) 0x4339d9 VDIVSD %XMM0,%XMM21,%XMM10 |
(226) 0x4339df VXORPD %XMM20,%XMM10,%XMM2 |
(226) 0x4339e5 VMULSD (%RDX),%XMM2,%XMM3 |
(226) 0x4339e9 JMP 4338d8 |
0x4339f0 MOV -0x5c(%RBP),%EAX |
0x4339f3 MOVB $0x1,-0x49(%RBP) |
0x4339f7 MOV %EAX,-0x50(%RBP) |
0x4339fa MOV -0x70(%RBP),%RDX |
0x4339fe MOV -0x40(%RBP),%RAX |
0x433a02 ADD %RDX,%R14 |
0x433a05 VMOVQ %XMM23,%RDX |
0x433a0b MOV %RAX,-0x58(%RBP) |
0x433a0f ADD %RDX,%R13 |
0x433a12 VMOVQ %XMM27,%RDX |
0x433a18 ADD %RDX,%R12 |
0x433a1b VMOVQ %XMM24,%RDX |
0x433a21 ADD %RDX,%R9 |
0x433a24 ADD %RDX,%R8 |
0x433a27 VMOVQ %XMM31,%RDX |
0x433a2d ADD %RDX,%RDI |
0x433a30 VMOVQ %XMM26,%RDX |
0x433a36 ADD %RDX,%RBX |
0x433a39 VMOVQ %XMM13,%RDX |
0x433a3e ADD %RDX,%RSI |
0x433a41 VMOVQ %XMM25,%RDX |
0x433a47 ADD %RDX,%R11 |
0x433a4a VMOVQ %XMM13,%RDX |
0x433a4f ADD %RDX,%RCX |
0x433a52 VMOVQ %XMM25,%RDX |
0x433a58 ADD %RDX,%R10 |
0x433a5b CMP %EAX,-0x64(%RBP) |
0x433a5e JLE 433aa0 |
0x433a60 INC %RAX |
0x433a63 MOV -0x68(%RBP),%EDX |
0x433a66 MOV %RAX,-0x40(%RBP) |
0x433a6a CMP %EDX,-0x60(%RBP) |
0x433a6d JLE 433860 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 93 - 129 |
-------------------------------------------------------------------------------- |
93: !$OMP SIMD |
94: DO j=x_min,x_max |
95: |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
124: dtdivt=dtdiv_safe*(-1.0_8/div) |
125: ELSE |
126: dtdivt=g_big |
127: ENDIF |
128: |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.47 |
CQA speedup if FP arith vectorized | 1.59 |
CQA speedup if fully vectorized | 5.79 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.15 |
Bottlenecks | micro-operation queue, |
Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
Source | calc_dt_kernel.f90:93-93,calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.83 |
CQA cycles if no scalar integer | 6.00 |
CQA cycles if FP arith vectorized | 5.54 |
CQA cycles if fully vectorized | 1.53 |
Front-end cycles | 8.83 |
DIV/SQRT cycles | 3.75 |
P0 cycles | 3.75 |
P1 cycles | 3.50 |
P2 cycles | 3.50 |
P3 cycles | 1.50 |
P4 cycles | 7.67 |
P5 cycles | 7.67 |
P6 cycles | 7.67 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.50 |
P10 cycles | 1.50 |
P11 cycles | 6.00 |
P12 cycles | 6.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 54.00 |
Nb uops | 53.00 |
Nb loads | 19.00 |
Nb stores | 4.00 |
Nb stack references | 11.00 |
FLOP/cycle | 0.45 |
Nb FLOP add-sub | 3.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.77 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 21.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 2.78 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 7.14 |
Vector-efficiency ratio all | 12.20 |
Vector-efficiency ratio load | 11.93 |
Vector-efficiency ratio store | 8.20 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.95 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.47 |
CQA speedup if FP arith vectorized | 1.59 |
CQA speedup if fully vectorized | 5.79 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.15 |
Bottlenecks | micro-operation queue, |
Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
Source | calc_dt_kernel.f90:93-93,calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.83 |
CQA cycles if no scalar integer | 6.00 |
CQA cycles if FP arith vectorized | 5.54 |
CQA cycles if fully vectorized | 1.53 |
Front-end cycles | 8.83 |
DIV/SQRT cycles | 3.75 |
P0 cycles | 3.75 |
P1 cycles | 3.50 |
P2 cycles | 3.50 |
P3 cycles | 1.50 |
P4 cycles | 7.67 |
P5 cycles | 7.67 |
P6 cycles | 7.67 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.50 |
P10 cycles | 1.50 |
P11 cycles | 6.00 |
P12 cycles | 6.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 54.00 |
Nb uops | 53.00 |
Nb loads | 19.00 |
Nb stores | 4.00 |
Nb stack references | 11.00 |
FLOP/cycle | 0.45 |
Nb FLOP add-sub | 3.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.77 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 21.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 2.78 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 7.14 |
Vector-efficiency ratio all | 12.20 |
Vector-efficiency ratio load | 11.93 |
Vector-efficiency ratio store | 8.20 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.95 |
Path / |
Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
Source file and lines | calc_dt_kernel.f90:93-129 |
Module | exec |
nb instructions | 54 |
nb uops | 53 |
loop length | 231 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 21 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
ADD-SUB / MUL ratio | 3.00 |
micro-operation queue | 8.83 cycles |
front end | 8.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.75 | 3.75 | 3.50 | 3.50 | 1.50 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 | 1.50 | 1.50 | 6.00 | 6.00 |
cycles | 3.75 | 3.75 | 3.50 | 3.50 | 1.50 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 | 1.50 | 1.50 | 6.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 8.83 |
Dispatch | 7.67 |
Overall L1 | 8.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 7% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 11% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 11% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x58(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ %XMM19,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%R9),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RCX),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD (%R8),%XMM4,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD (%RSI),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD (%RDI),%XMM2,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSD (%RAX,%RDX,8),%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV -0x80(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD (%RAX),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDX),%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM29,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM28,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RAX),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDX),%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM20,%XMM11,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDSD %XMM15,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4338f5 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x415> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x5c(%RBP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOVB $0x1,-0x49(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RDX,%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM23,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RDX,%R13 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM27,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM24,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %RDX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM31,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM26,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM25,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM25,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %EAX,-0x64(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 433aa0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x5c0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
INC %RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x68(%RBP),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,-0x60(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 433860 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x380> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0 |
Source file and lines | calc_dt_kernel.f90:93-129 |
Module | exec |
nb instructions | 54 |
nb uops | 53 |
loop length | 231 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 21 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
ADD-SUB / MUL ratio | 3.00 |
micro-operation queue | 8.83 cycles |
front end | 8.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.75 | 3.75 | 3.50 | 3.50 | 1.50 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 | 1.50 | 1.50 | 6.00 | 6.00 |
cycles | 3.75 | 3.75 | 3.50 | 3.50 | 1.50 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 | 1.50 | 1.50 | 6.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 8.83 |
Dispatch | 7.67 |
Overall L1 | 8.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 7% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 11% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 11% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x58(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ %XMM19,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%R9),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RCX),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD (%R8),%XMM4,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD (%RSI),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD (%RDI),%XMM2,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSD (%RAX,%RDX,8),%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV -0x80(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD (%RAX),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDX),%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM29,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM28,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RAX),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDX),%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VXORPD %XMM20,%XMM11,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VADDSD %XMM15,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4338f5 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x415> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x5c(%RBP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOVB $0x1,-0x49(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EAX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RDX,%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM23,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD %RDX,%R13 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM27,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM24,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %RDX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM31,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM26,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM25,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVQ %XMM25,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD %RDX,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %EAX,-0x64(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 433aa0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x5c0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
INC %RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x68(%RBP),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,-0x60(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 433860 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0.lto_priv.0+0x380> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |