Loop Id: 116 | Module: exec | Source: advec_mom_kernel.f90:106-107 | Coverage: 2.53% |
---|
Loop Id: 116 | Module: exec | Source: advec_mom_kernel.f90:106-107 | Coverage: 2.53% |
---|
0x4223ee VMOVUPD (%R15,%RAX,1),%ZMM0 [1] |
0x4223f5 VMOVUPD %ZMM0,(%R14,%RAX,1) [3] |
0x4223fc VADDPD (%R12,%RAX,1),%ZMM0,%ZMM3 [4] |
0x422403 VSUBPD (%R11,%RAX,1),%ZMM3,%ZMM11 [2] |
0x42240a VMOVUPD %ZMM11,(%R10,%RAX,1) [5] |
0x422411 VMOVUPD 0x40(%R15,%RAX,1),%ZMM12 [1] |
0x422419 VMOVUPD %ZMM12,0x40(%R14,%RAX,1) [3] |
0x422421 VADDPD 0x40(%R12,%RAX,1),%ZMM12,%ZMM13 [4] |
0x422429 VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 [2] |
0x422431 VMOVUPD %ZMM14,0x40(%R10,%RAX,1) [5] |
0x422439 VMOVUPD 0x80(%R15,%RAX,1),%ZMM5 [1] |
0x422441 VMOVUPD %ZMM5,0x80(%R14,%RAX,1) [3] |
0x422449 VADDPD 0x80(%R12,%RAX,1),%ZMM5,%ZMM15 [4] |
0x422451 VSUBPD 0x80(%R11,%RAX,1),%ZMM15,%ZMM1 [2] |
0x422459 VMOVUPD %ZMM1,0x80(%R10,%RAX,1) [5] |
0x422461 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM0 [1] |
0x422469 VMOVUPD %ZMM0,0xc0(%R14,%RAX,1) [3] |
0x422471 VADDPD 0xc0(%R12,%RAX,1),%ZMM0,%ZMM3 [4] |
0x422479 VSUBPD 0xc0(%R11,%RAX,1),%ZMM3,%ZMM11 [2] |
0x422481 VMOVUPD %ZMM11,0xc0(%R10,%RAX,1) [5] |
0x422489 VMOVUPD 0x100(%R15,%RAX,1),%ZMM12 [1] |
0x422491 VMOVUPD %ZMM12,0x100(%R14,%RAX,1) [3] |
0x422499 VADDPD 0x100(%R12,%RAX,1),%ZMM12,%ZMM13 [4] |
0x4224a1 VSUBPD 0x100(%R11,%RAX,1),%ZMM13,%ZMM14 [2] |
0x4224a9 VMOVUPD %ZMM14,0x100(%R10,%RAX,1) [5] |
0x4224b1 VMOVUPD 0x140(%R15,%RAX,1),%ZMM5 [1] |
0x4224b9 VMOVUPD %ZMM5,0x140(%R14,%RAX,1) [3] |
0x4224c1 VADDPD 0x140(%R12,%RAX,1),%ZMM5,%ZMM15 [4] |
0x4224c9 VSUBPD 0x140(%R11,%RAX,1),%ZMM15,%ZMM1 [2] |
0x4224d1 VMOVUPD %ZMM1,0x140(%R10,%RAX,1) [5] |
0x4224d9 VMOVUPD 0x180(%R15,%RAX,1),%ZMM0 [1] |
0x4224e1 VMOVUPD %ZMM0,0x180(%R14,%RAX,1) [3] |
0x4224e9 VADDPD 0x180(%R12,%RAX,1),%ZMM0,%ZMM3 [4] |
0x4224f1 MOV 0x148(%RSP),%RDX [6] |
0x4224f9 VSUBPD 0x180(%R11,%RAX,1),%ZMM3,%ZMM11 [2] |
0x422501 VMOVUPD %ZMM11,0x180(%R10,%RAX,1) [5] |
0x422509 VMOVUPD 0x1c0(%R15,%RAX,1),%ZMM12 [1] |
0x422511 VMOVUPD %ZMM12,0x1c0(%R14,%RAX,1) [3] |
0x422519 VADDPD 0x1c0(%R12,%RAX,1),%ZMM12,%ZMM13 [4] |
0x422521 VSUBPD 0x1c0(%R11,%RAX,1),%ZMM13,%ZMM14 [2] |
0x422529 VMOVUPD %ZMM14,0x1c0(%R10,%RAX,1) [5] |
0x422531 ADD $0x200,%RAX |
0x422537 CMP %RDX,%RAX |
0x42253a JNE 4223ee |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 106 - 107 |
-------------------------------------------------------------------------------- |
106: post_vol(j,k)=volume(j,k) |
107: pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | P5, P6, P7, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:106-107 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.67 |
CQA cycles if no scalar integer | 21.67 |
CQA cycles if FP arith vectorized | 21.67 |
CQA cycles if fully vectorized | 21.67 |
Front-end cycles | 9.83 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 21.67 |
P5 cycles | 21.67 |
P6 cycles | 21.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 16.00 |
P10 cycles | 16.00 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 44.00 |
Nb uops | 59.00 |
Nb loads | 25.00 |
Nb stores | 16.00 |
Nb stack references | 1.00 |
FLOP/cycle | 5.91 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 118.52 |
Bytes prefetched | 0.00 |
Bytes loaded | 1544.00 |
Bytes stored | 1024.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | P5, P6, P7, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:106-107 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.67 |
CQA cycles if no scalar integer | 21.67 |
CQA cycles if FP arith vectorized | 21.67 |
CQA cycles if fully vectorized | 21.67 |
Front-end cycles | 9.83 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 21.67 |
P5 cycles | 21.67 |
P6 cycles | 21.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 16.00 |
P10 cycles | 16.00 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 44.00 |
Nb uops | 59.00 |
Nb loads | 25.00 |
Nb stores | 16.00 |
Nb stack references | 1.00 |
FLOP/cycle | 5.91 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 118.52 |
Bytes prefetched | 0.00 |
Bytes loaded | 1544.00 |
Bytes stored | 1024.00 |
Stride 0 | 1.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:106-107 |
Module | exec |
nb instructions | 44 |
nb uops | 59 |
loop length | 338 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 9 |
nb stack references | 1 |
micro-operation queue | 9.83 cycles |
front end | 9.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 13.67 | 13.67 | 13.67 | 0.00 | 0.00 | 8.00 | 8.00 | 16.00 | 16.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 21.67 | 21.67 | 21.67 | 0.00 | 0.00 | 16.00 | 16.00 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 9.83 |
Dispatch | 21.67 |
Data deps. | 1.00 |
Overall L1 | 21.67 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R15,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD (%R12,%RAX,1),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%R11,%RAX,1),%ZMM3,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R15,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x40(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x40(%R12,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x40(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R15,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM5,0x80(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x80(%R12,%RAX,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R11,%RAX,1),%ZMM15,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0x80(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R15,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0xc0(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0xc0(%R12,%RAX,1),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R11,%RAX,1),%ZMM3,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,0xc0(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x100(%R15,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x100(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x100(%R12,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x100(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x100(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x140(%R15,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM5,0x140(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x140(%R12,%RAX,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x140(%R11,%RAX,1),%ZMM15,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0x140(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x180(%R15,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x180(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x180(%R12,%RAX,1),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x148(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VSUBPD 0x180(%R11,%RAX,1),%ZMM3,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,0x180(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x1c0(%R15,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x1c0(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x1c0(%R12,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x1c0(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x1c0(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 4223ee <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3bae> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:106-107 |
Module | exec |
nb instructions | 44 |
nb uops | 59 |
loop length | 338 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 9 |
nb stack references | 1 |
micro-operation queue | 9.83 cycles |
front end | 9.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 13.67 | 13.67 | 13.67 | 0.00 | 0.00 | 8.00 | 8.00 | 16.00 | 16.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 21.67 | 21.67 | 21.67 | 0.00 | 0.00 | 16.00 | 16.00 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 9.83 |
Dispatch | 21.67 |
Data deps. | 1.00 |
Overall L1 | 21.67 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R15,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD (%R12,%RAX,1),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%R11,%RAX,1),%ZMM3,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R15,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x40(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x40(%R12,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x40(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R15,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM5,0x80(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x80(%R12,%RAX,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R11,%RAX,1),%ZMM15,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0x80(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R15,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0xc0(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0xc0(%R12,%RAX,1),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R11,%RAX,1),%ZMM3,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,0xc0(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x100(%R15,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x100(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x100(%R12,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x100(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x100(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x140(%R15,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM5,0x140(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x140(%R12,%RAX,1),%ZMM5,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x140(%R11,%RAX,1),%ZMM15,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0x140(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x180(%R15,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x180(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x180(%R12,%RAX,1),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
MOV 0x148(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VSUBPD 0x180(%R11,%RAX,1),%ZMM3,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,0x180(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x1c0(%R15,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x1c0(%R14,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x1c0(%R12,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x1c0(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x1c0(%R10,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 4223ee <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3bae> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |