Loop Id: 163 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 0.02% |
---|
Loop Id: 163 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 0.02% |
---|
0x430170 MOV 0x10(%RSP),%RDI |
0x430175 LEA 0x1(%RDI),%RAX |
0x430179 MOV 0x158(%RSP),%RCX |
0x430181 MOV 0x60(%RSP),%R9 |
0x430186 ADD %RCX,%R9 |
0x430189 MOV 0x140(%RSP),%RDX |
0x430191 MOV 0x50(%RSP),%R15 |
0x430196 ADD %RDX,%R15 |
0x430199 ADD %RCX,0x30(%RSP) |
0x43019e ADD %RDX,0x220(%RSP) |
0x4301a6 CMP 0xd8(%RSP),%RDI |
0x4301ae MOV %RAX,0x10(%RSP) |
0x4301b3 MOV 0x58(%RSP),%R14 |
0x4301b8 JE 42d7a0 |
0x4301be TEST %R14,%R14 |
0x4301c1 MOV %R15,0x50(%RSP) |
0x4301c6 MOV %R9,0x60(%RSP) |
0x4301cb JE 4303c0 |
0x4301d1 MOV 0x40(%RSP),%RAX |
0x4301d6 MOV 0x10(%RSP),%RCX |
0x4301db ADD %RAX,%RCX |
0x4301de SUB 0x18(%RSP),%RCX |
0x4301e3 MOV 0x48(%RSP),%RDX |
0x4301e8 IMUL %RCX,%RDX |
0x4301ec IMUL 0x38(%RSP),%RCX |
0x4301f2 ADD 0xc8(%RSP),%RDX |
0x4301fa ADD 0x130(%RSP),%RCX |
0x430202 XOR %EDI,%EDI |
0x430204 MOV 0x1e0(%RSP),%R8 |
0x43020c MOV 0xf0(%RSP),%R10 |
0x430214 NOPW %CS:(%RAX,%RAX,1) |
(165) 0x430220 VMOVUPD (%R15,%RDI,8),%YMM18 |
(165) 0x430227 VCMPPD $0x1,%YMM16,%YMM18,%K1 |
(165) 0x43022e LEA (%RDI,%R13,1),%EAX |
(165) 0x430232 VPBROADCASTD %EAX,%XMM19 |
(165) 0x430238 VPADDD %XMM8,%XMM19,%XMM20 |
(165) 0x43023e VPADDD %XMM9,%XMM19,%XMM21 |
(165) 0x430244 VPADDD %XMM10,%XMM19,%XMM22 |
(165) 0x43024a VPBLENDMD %XMM22,%XMM20,%XMM23{%K1} |
(165) 0x430250 VMOVDQA32 %XMM20,%XMM22{%K1} |
(165) 0x430256 VPMOVSXDQ %XMM22,%YMM22 |
(165) 0x43025c VPSUBQ %YMM0,%YMM22,%YMM22 |
(165) 0x430262 KXNORW %K0,%K0,%K2 |
(165) 0x430266 VXORPD %XMM24,%XMM24,%XMM24 |
(165) 0x43026c VGATHERQPD (%RDX,%YMM22,8),%YMM24{%K2} |
(165) 0x430273 KXNORW %K0,%K0,%K2 |
(165) 0x430277 VXORPD %XMM25,%XMM25,%XMM25 |
(165) 0x43027d VGATHERQPD (%RCX,%YMM22,8),%YMM25{%K2} |
(165) 0x430284 VPBLENDMD %XMM20,%XMM21,%XMM20{%K1} |
(165) 0x43028a VPADDD %XMM11,%XMM19,%XMM21{%K1} |
(165) 0x430290 VANDPD %YMM12,%YMM18,%YMM19 |
(165) 0x430296 VPMOVSXDQ %XMM21,%YMM21 |
(165) 0x43029c VPSUBQ %YMM0,%YMM21,%YMM21 |
(165) 0x4302a2 KXNORW %K0,%K0,%K1 |
(165) 0x4302a6 VXORPD %XMM22,%XMM22,%XMM22 |
(165) 0x4302ac VGATHERQPD (%RCX,%YMM21,8),%YMM22{%K1} |
(165) 0x4302b3 VDIVPD %YMM24,%YMM19,%YMM19 |
(165) 0x4302b9 VSUBPD %YMM22,%YMM25,%YMM21 |
(165) 0x4302bf VPMOVSXDQ %XMM23,%YMM22 |
(165) 0x4302c5 VPSUBQ %YMM0,%YMM22,%YMM22 |
(165) 0x4302cb KXNORW %K0,%K0,%K1 |
(165) 0x4302cf VPXORD %XMM23,%XMM23,%XMM23 |
(165) 0x4302d5 VGATHERQPD (%RCX,%YMM22,8),%YMM23{%K1} |
(165) 0x4302dc VSUBPD %YMM25,%YMM23,%YMM22 |
(165) 0x4302e2 VMULPD %YMM21,%YMM22,%YMM23 |
(165) 0x4302e8 VCMPPD $0x1,%YMM23,%YMM16,%K1 |
(165) 0x4302ef VMOVUPD (%R10,%RDI,8),%YMM23{%K1}{z} |
(165) 0x4302f6 VANDPD %YMM12,%YMM21,%YMM21 |
(165) 0x4302fc VANDPD %YMM12,%YMM22,%YMM24 |
(165) 0x430302 VSUBPD %YMM19,%YMM13,%YMM26 |
(165) 0x430308 VMULPD %YMM26,%YMM24,%YMM26 |
(165) 0x43030e VDIVPD %YMM23,%YMM26,%YMM26 |
(165) 0x430314 VPMOVSXDQ %XMM20,%YMM20 |
(165) 0x43031a VPSUBQ %YMM0,%YMM20,%YMM20 |
(165) 0x430320 KMOVQ %K1,%K2 |
(165) 0x430325 VXORPD %XMM27,%XMM27,%XMM27 |
(165) 0x43032b VGATHERQPD (%R8,%YMM20,8),%YMM27{%K2} |
(165) 0x430332 VCMPPD $0x2,%YMM24,%YMM21,%K2 |
(165) 0x430339 VMOVAPD %YMM21,%YMM24{%K2} |
(165) 0x43033f VFMADD213PD %YMM21,%YMM19,%YMM21 |
(165) 0x430345 VDIVPD %YMM27,%YMM21,%YMM20 |
(165) 0x43034b VADDPD %YMM26,%YMM20,%YMM20 |
(165) 0x430351 VMULPD %YMM15,%YMM23,%YMM21 |
(165) 0x430357 VMULPD %YMM20,%YMM21,%YMM20 |
(165) 0x43035d VCMPPD $0x2,%YMM24,%YMM20,%K2 |
(165) 0x430364 VMOVAPD %YMM20,%YMM24{%K2} |
(165) 0x43036a VCMPPD $0x2,%YMM16,%YMM22,%K2 |
(165) 0x430371 VXORPD %YMM17,%YMM24,%YMM24{%K2} |
(165) 0x430377 VMOVAPD %YMM24,%YMM20{%K1}{z} |
(165) 0x43037d VSUBPD %YMM19,%YMM14,%YMM19 |
(165) 0x430383 VFMADD213PD %YMM25,%YMM20,%YMM19 |
(165) 0x430389 VMULPD %YMM18,%YMM19,%YMM18 |
(165) 0x43038f VMOVUPD %YMM18,(%R9,%RDI,8) |
(165) 0x430396 ADD $0x4,%RDI |
(165) 0x43039a CMP %R14,%RDI |
(165) 0x43039d JL 430220 |
0x4303a3 MOV %R14,%R9 |
0x4303a6 CMP %R14,0x20(%RSP) |
0x4303ab JE 430170 |
0x4303b1 JMP 4303c3 |
0x4303c0 XOR %R9D,%R9D |
0x4303c3 MOV 0x40(%RSP),%RAX |
0x4303c8 MOV 0x10(%RSP),%RCX |
0x4303cd LEA (%RAX,%RCX,1),%R11 |
0x4303d1 SUB 0x18(%RSP),%R11 |
0x4303d6 MOV 0x48(%RSP),%RBX |
0x4303db IMUL %R11,%RBX |
0x4303df ADD 0xc8(%RSP),%RBX |
0x4303e7 IMUL 0x38(%RSP),%R11 |
0x4303ed ADD 0x130(%RSP),%R11 |
0x4303f5 MOV 0x110(%RSP),%RAX |
0x4303fd LEA (%RAX,%R9,1),%R8D |
0x430401 MOV 0xf8(%RSP),%RAX |
0x430409 ADD %R9,%RAX |
0x43040c MOV 0x30(%RSP),%RCX |
0x430411 LEA (%RCX,%RAX,8),%R12 |
0x430415 MOV 0x118(%RSP),%RCX |
0x43041d LEA (%RCX,%RAX,8),%RCX |
0x430421 MOV %RCX,0x240(%RSP) |
0x430429 MOV 0x220(%RSP),%RCX |
0x430431 LEA (%RCX,%RAX,8),%RDI |
0x430435 MOV 0x20(%RSP),%R10 |
0x43043a SUB %R9,%R10 |
0x43043d MOV 0x108(%RSP),%RAX |
0x430445 ADD %R9D,%EAX |
0x430448 MOV %RAX,0x1c0(%RSP) |
0x430450 XOR %R15D,%R15D |
0x430453 JMP 430488 |
(164) 0x430460 VSUBSD %XMM20,%XMM7,%XMM20 |
(164) 0x430466 VFMADD213SD %XMM19,%XMM21,%XMM20 |
(164) 0x43046c VMULSD %XMM18,%XMM20,%XMM18 |
(164) 0x430472 VMOVSD %XMM18,(%R12,%R15,8) |
(164) 0x430479 INC %R9 |
(164) 0x43047c INC %R15 |
(164) 0x43047f CMP %R15,%R10 |
(164) 0x430482 JE 430170 |
(164) 0x430488 VMOVSD (%RDI,%R15,8),%XMM18 |
(164) 0x43048f LEA (%R9,%R13,1),%ECX |
(164) 0x430493 LEA (%R8,%R15,1),%R14 |
(164) 0x430497 VUCOMISD %XMM18,%XMM1 |
(164) 0x43049d JBE 4304b0 |
(164) 0x43049f LEA 0x1(%RCX),%EAX |
(164) 0x4304a2 MOV %ECX,%EDX |
(164) 0x4304a4 JMP 4304c3 |
(164) 0x4304b0 MOV 0x1c0(%RSP),%RAX |
(164) 0x4304b8 ADD %R15D,%EAX |
(164) 0x4304bb MOV %R14D,%EDX |
(164) 0x4304be MOV %ECX,%R14D |
(164) 0x4304c1 MOV %EAX,%ECX |
(164) 0x4304c3 VANDPD %XMM2,%XMM18,%XMM19 |
(164) 0x4304c9 MOVSXD %EDX,%RDX |
(164) 0x4304cc SUB %RSI,%RDX |
(164) 0x4304cf VDIVSD (%RBX,%RDX,8),%XMM19,%XMM20 |
(164) 0x4304d6 VMOVSD (%R11,%RDX,8),%XMM19 |
(164) 0x4304dd CLTQ |
(164) 0x4304df SUB %RSI,%RAX |
(164) 0x4304e2 VSUBSD (%R11,%RAX,8),%XMM19,%XMM23 |
(164) 0x4304e9 MOVSXD %R14D,%RAX |
(164) 0x4304ec SUB %RSI,%RAX |
(164) 0x4304ef VMOVSD (%R11,%RAX,8),%XMM21 |
(164) 0x4304f6 VSUBSD %XMM19,%XMM21,%XMM22 |
(164) 0x4304fc VMULSD %XMM23,%XMM22,%XMM24 |
(164) 0x430502 VXORPD %XMM21,%XMM21,%XMM21 |
(164) 0x430508 VUCOMISD %XMM21,%XMM24 |
(164) 0x43050e JBE 430460 |
(164) 0x430514 MOV 0x240(%RSP),%RAX |
(164) 0x43051c VMOVSD (%RAX,%R15,8),%XMM24 |
(164) 0x430523 VANDPD %XMM3,%XMM23,%XMM23 |
(164) 0x430529 VANDPD %XMM3,%XMM22,%XMM21 |
(164) 0x43052f VSUBSD %XMM20,%XMM4,%XMM25 |
(164) 0x430535 VMULSD %XMM25,%XMM21,%XMM25 |
(164) 0x43053b VDIVSD %XMM24,%XMM25,%XMM25 |
(164) 0x430541 VCMPSD $0x2,%XMM21,%XMM23,%K1 |
(164) 0x430548 VMOVSD %XMM23,%XMM21,%XMM21{%K1} |
(164) 0x43054e VFMADD213SD %XMM23,%XMM20,%XMM23 |
(164) 0x430554 MOVSXD %ECX,%RAX |
(164) 0x430557 SUB %RSI,%RAX |
(164) 0x43055a MOV 0x1e0(%RSP),%RCX |
(164) 0x430562 VDIVSD (%RCX,%RAX,8),%XMM23,%XMM23 |
(164) 0x430569 VADDSD %XMM25,%XMM23,%XMM23 |
(164) 0x43056f VMULSD %XMM5,%XMM24,%XMM24 |
(164) 0x430575 VMULSD %XMM23,%XMM24,%XMM23 |
(164) 0x43057b VCMPSD $0x2,%XMM21,%XMM23,%K1 |
(164) 0x430582 VMOVSD %XMM23,%XMM21,%XMM21{%K1} |
(164) 0x430588 VXORPD %XMM6,%XMM21,%XMM23 |
(164) 0x43058e VCMPSD $0x2,%XMM1,%XMM22,%K1 |
(164) 0x430595 VMOVSD %XMM23,%XMM21,%XMM21{%K1} |
(164) 0x43059b JMP 430460 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 177 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
150: DO k=y_min,y_max+1 |
151: DO j=x_min-1,x_max+1 |
152: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
158: upwind=j-1 |
159: donor=j |
160: downwind=j+1 |
161: dif=upwind |
162: ENDIF |
163: sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k)) |
164: width=celldx(j) |
165: vdiffuw=vel1(donor,k)-vel1(upwind,k) |
166: vdiffdw=vel1(downwind,k)-vel1(donor,k) |
167: limiter=0.0 |
168: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
169: auw=ABS(vdiffuw) |
170: adw=ABS(vdiffdw) |
171: wind=1.0_8 |
172: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
173: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw) |
174: ENDIF |
175: advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter |
176: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
177: ENDDO |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.41 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.19 |
Bottlenecks | P5, P6, P7, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:150-152,advec_mom_kernel.f90:163-165,advec_mom_kernel.f90:177-177 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.67 |
CQA cycles if no scalar integer | 12.67 |
CQA cycles if FP arith vectorized | 12.67 |
CQA cycles if fully vectorized | 2.88 |
Front-end cycles | 10.67 |
DIV/SQRT cycles | 7.50 |
P0 cycles | 7.50 |
P1 cycles | 7.25 |
P2 cycles | 7.25 |
P3 cycles | 2.50 |
P4 cycles | 12.67 |
P5 cycles | 12.67 |
P6 cycles | 12.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 63.00 |
Nb uops | 64.00 |
Nb loads | 33.00 |
Nb stores | 7.00 |
Nb stack references | 24.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.26 |
Bytes prefetched | 0.00 |
Bytes loaded | 264.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.28 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.94 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.41 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.19 |
Bottlenecks | P5, P6, P7, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:150-152,advec_mom_kernel.f90:163-165,advec_mom_kernel.f90:177-177 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.67 |
CQA cycles if no scalar integer | 12.67 |
CQA cycles if FP arith vectorized | 12.67 |
CQA cycles if fully vectorized | 2.88 |
Front-end cycles | 10.67 |
DIV/SQRT cycles | 7.50 |
P0 cycles | 7.50 |
P1 cycles | 7.25 |
P2 cycles | 7.25 |
P3 cycles | 2.50 |
P4 cycles | 12.67 |
P5 cycles | 12.67 |
P6 cycles | 12.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 63.00 |
Nb uops | 64.00 |
Nb loads | 33.00 |
Nb stores | 7.00 |
Nb stack references | 24.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.26 |
Bytes prefetched | 0.00 |
Bytes loaded | 264.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.28 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.94 |
Path / |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-177 |
Module | exec |
nb instructions | 63 |
nb uops | 64 |
loop length | 341 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 24 |
micro-operation queue | 10.67 cycles |
front end | 10.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 7.50 | 7.25 | 7.25 | 2.50 | 12.67 | 12.67 | 12.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.50 | 7.50 | 7.25 | 7.25 | 2.50 | 12.67 | 12.67 | 12.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 10.67 |
Dispatch | 12.67 |
Overall L1 | 12.67 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x10(%RSP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%RDI),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x158(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x60(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RCX,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x140(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x50(%RSP),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RDX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %RCX,0x30(%RSP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %RDX,0x220(%RSP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP 0xd8(%RSP),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x58(%RSP),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JE 42d7a0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x8c0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R15,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R9,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JE 4303c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x34e0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV 0x40(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RAX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB 0x18(%RSP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV 0x48(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %RCX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL 0x38(%RSP),%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xc8(%RSP),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
ADD 0x130(%RSP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x1e0(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0xf0(%RSP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R14,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R14,0x20(%RSP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 430170 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3290> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
JMP 4303c3 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x34e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x40(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RAX,%RCX,1),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB 0x18(%RSP),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R11,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xc8(%RSP),%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
IMUL 0x38(%RSP),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x130(%RSP),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV 0x110(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RAX,%R9,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %R9,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x30(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,8),%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x118(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,8),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RCX,0x240(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x220(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,8),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x20(%RSP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB %R9,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x108(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %R9D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RAX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 430488 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x35a8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-177 |
Module | exec |
nb instructions | 63 |
nb uops | 64 |
loop length | 341 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 24 |
micro-operation queue | 10.67 cycles |
front end | 10.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 7.50 | 7.25 | 7.25 | 2.50 | 12.67 | 12.67 | 12.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.50 | 7.50 | 7.25 | 7.25 | 2.50 | 12.67 | 12.67 | 12.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 10.67 |
Dispatch | 12.67 |
Overall L1 | 12.67 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0x10(%RSP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%RDI),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x158(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x60(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RCX,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x140(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x50(%RSP),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RDX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %RCX,0x30(%RSP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %RDX,0x220(%RSP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP 0xd8(%RSP),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x58(%RSP),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JE 42d7a0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x8c0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
TEST %R14,%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R15,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R9,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JE 4303c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x34e0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV 0x40(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RAX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB 0x18(%RSP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV 0x48(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %RCX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL 0x38(%RSP),%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xc8(%RSP),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
ADD 0x130(%RSP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x1e0(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0xf0(%RSP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R14,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R14,0x20(%RSP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 430170 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3290> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
JMP 4303c3 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x34e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x40(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RAX,%RCX,1),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB 0x18(%RSP),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R11,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xc8(%RSP),%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
IMUL 0x38(%RSP),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x130(%RSP),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV 0x110(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RAX,%R9,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %R9,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x30(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,8),%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x118(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,8),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RCX,0x240(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x220(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%RCX,%RAX,8),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x20(%RSP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB %R9,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x108(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %R9D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RAX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 430488 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x35a8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |