Loop Id: 174 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 4.29% |
---|
Loop Id: 174 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 4.29% |
---|
0x4308d0 VANDPD %YMM10,%YMM26,%YMM7 |
0x4308d6 VPMULLQ %YMM30,%YMM1,%YMM30 |
0x4308dc VPADDQ %YMM31,%YMM0,%YMM31 |
0x4308e2 VPADDQ %YMM30,%YMM31,%YMM30 |
0x4308e8 VPXORD %XMM31,%XMM31,%XMM31 |
0x4308ee KXNORW %K0,%K0,%K3 |
0x4308f2 VGATHERQPD (,%YMM30,1),%YMM31{%K3} [3] |
0x4308fd VDIVPD %YMM31,%YMM7,%YMM7 |
0x430903 VPBLENDMD %XMM23,%XMM22,%XMM30{%K1} |
0x430909 VANDPD %YMM10,%YMM8,%YMM8 |
0x43090e VANDPD %YMM10,%YMM28,%YMM31 |
0x430914 VSUBPD %YMM7,%YMM11,%YMM16 |
0x43091a VMULPD %YMM16,%YMM31,%YMM16 |
0x430920 VDIVSD %XMM29,%XMM12,%XMM17 |
0x430926 VBROADCASTSD %XMM17,%YMM17 |
0x43092c VCMPPD $0x2,%YMM31,%YMM8,%K1 |
0x430933 VMOVAPD %YMM8,%YMM31{%K1} |
0x430939 VPMOVSXDQ %XMM30,%YMM30 |
0x43093f VPSUBQ %YMM3,%YMM30,%YMM30 |
0x430945 KMOVQ %K2,%K1 |
0x43094a VXORPD %XMM18,%XMM18,%XMM18 |
0x430950 VGATHERQPD (%R15,%YMM30,8),%YMM18{%K1} [2] |
0x430957 VFMADD213PD %YMM8,%YMM7,%YMM8 |
0x43095c VDIVPD %YMM18,%YMM8,%YMM8 |
0x430962 VFMADD231PD %YMM17,%YMM16,%YMM8 |
0x430968 VMULSD %XMM14,%XMM29,%XMM16 |
0x43096e VBROADCASTSD %XMM16,%YMM16 |
0x430974 VMULPD %YMM8,%YMM16,%YMM8 |
0x43097a VCMPPD $0x2,%YMM31,%YMM8,%K1 |
0x430981 VMOVAPD %YMM8,%YMM31{%K1} |
0x430987 VCMPPD $0x2,%YMM9,%YMM28,%K1 |
0x43098e VXORPD %YMM15,%YMM31,%YMM31{%K1} |
0x430994 VMOVAPD %YMM31,%YMM8{%K2}{z} |
0x43099a VSUBPD %YMM7,%YMM13,%YMM7 |
0x43099e VFMADD213PD %YMM27,%YMM8,%YMM7 |
0x4309a4 VMULPD %YMM26,%YMM7,%YMM7 |
0x4309aa VMOVUPD %YMM7,(%R14,%RDX,8) [6] |
0x4309b0 ADD $0x4,%RDX |
0x4309b4 CMP %R9,%RDX |
0x4309b7 JGE 430ab0 |
0x4309bd VMOVUPD (%R13,%RDX,8),%YMM26 [1] |
0x4309c5 VCMPPD $0x1,%YMM9,%YMM26,%K1 |
0x4309cc VPBLENDMD %XMM23,%XMM25,%XMM8{%K1} |
0x4309d2 VPMOVSXDQ %XMM8,%YMM8 |
0x4309d7 VPSUBQ %YMM3,%YMM8,%YMM30 |
0x4309dd VPBROADCASTQ %RDX,%YMM8 |
0x4309e3 VPADDQ %YMM2,%YMM8,%YMM8 |
0x4309e7 VPSUBQ %YMM4,%YMM8,%YMM8 |
0x4309eb VPSLLQ $0x3,%YMM8,%YMM31 |
0x4309f2 VPMULLQ %YMM30,%YMM6,%YMM8 |
0x4309f8 VPADDQ %YMM31,%YMM5,%YMM28 |
0x4309fe VPADDQ %YMM8,%YMM28,%YMM8 |
0x430a04 VXORPD %XMM27,%XMM27,%XMM27 |
0x430a0a KXNORW %K0,%K0,%K2 |
0x430a0e VGATHERQPD (,%YMM8,1),%YMM27{%K2} [8] |
0x430a19 VPBLENDMD %XMM24,%XMM22,%XMM8{%K1} |
0x430a1f VPBLENDMD %XMM25,%XMM23,%XMM29{%K1} |
0x430a25 VPMOVSXDQ %XMM8,%YMM8 |
0x430a2a VPSUBQ %YMM3,%YMM8,%YMM8 |
0x430a2e VPMULLQ %YMM8,%YMM6,%YMM8 |
0x430a34 VPADDQ %YMM8,%YMM28,%YMM8 |
0x430a3a VXORPD %XMM7,%XMM7,%XMM7 |
0x430a3e KXNORW %K0,%K0,%K2 |
0x430a42 VGATHERQPD (,%YMM8,1),%YMM7{%K2} [7] |
0x430a4d VPMOVSXDQ %XMM29,%YMM8 |
0x430a53 VPSUBQ %YMM3,%YMM8,%YMM8 |
0x430a57 VPMULLQ %YMM8,%YMM6,%YMM8 |
0x430a5d VPADDQ %YMM8,%YMM28,%YMM8 |
0x430a63 VPXORD %XMM28,%XMM28,%XMM28 |
0x430a69 KXNORW %K0,%K0,%K2 |
0x430a6d VGATHERQPD (,%YMM8,1),%YMM28{%K2} [4] |
0x430a78 VSUBPD %YMM7,%YMM27,%YMM8 |
0x430a7e VSUBPD %YMM27,%YMM28,%YMM28 |
0x430a84 VMULPD %YMM8,%YMM28,%YMM7 |
0x430a8a VCMPPD $0x1,%YMM7,%YMM9,%K2 |
0x430a91 KORTESTB %K2,%K2 |
0x430a95 JE 4308d0 |
0x430a9b VMOVSD (%R15,%RSI,8),%XMM29 [5] |
0x430aa2 JMP 4308d0 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-861-0321/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 241 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
215: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
227: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
228: width=celldy(k) |
229: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
230: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
231: limiter=0.0 |
232: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
233: auw=ABS(vdiffuw) |
234: adw=ABS(vdiffdw) |
235: wind=1.0_8 |
236: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
237: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
238: ENDIF |
239: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
240: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
241: ENDDO |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.04 |
CQA speedup if FP arith vectorized | 1.68 |
CQA speedup if fully vectorized | 2.89 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.51 |
Bottlenecks | |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.50 |
CQA cycles if no scalar integer | 31.25 |
CQA cycles if FP arith vectorized | 19.40 |
CQA cycles if fully vectorized | 11.25 |
Front-end cycles | 32.50 |
DIV/SQRT cycles | 1.25 |
P0 cycles | 0.75 |
P1 cycles | 0.75 |
P2 cycles | 0.50 |
P3 cycles | 1.25 |
P4 cycles | 0.83 |
P5 cycles | 0.83 |
P6 cycles | 0.83 |
P7 cycles | 21.50 |
P8 cycles | 21.42 |
P9 cycles | 21.58 |
P10 cycles | 21.50 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 15.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 78.00 |
Nb uops | 195.00 |
Nb loads | 6.50 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.03 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 17.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 9.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.01 |
Bytes prefetched | 0.00 |
Bytes loaded | 196.00 |
Bytes stored | 32.00 |
Stride 0 | 0.50 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 91.86 |
Vectorization ratio load | 92.86 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 88.89 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 66.67 |
Vectorization ratio other | 91.18 |
Vector-efficiency ratio all | 42.13 |
Vector-efficiency ratio load | 47.32 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 45.83 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 37.50 |
Vector-efficiency ratio other | 37.13 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.04 |
CQA speedup if FP arith vectorized | 1.68 |
CQA speedup if fully vectorized | 2.90 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.51 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.67 |
CQA cycles if no scalar integer | 31.33 |
CQA cycles if FP arith vectorized | 19.49 |
CQA cycles if fully vectorized | 11.25 |
Front-end cycles | 32.67 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.75 |
P1 cycles | 0.75 |
P2 cycles | 0.50 |
P3 cycles | 1.50 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 21.50 |
P8 cycles | 21.42 |
P9 cycles | 21.58 |
P10 cycles | 21.50 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 15.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 79.00 |
Nb uops | 196.00 |
Nb loads | 7.00 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.02 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 17.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 9.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.10 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 32.00 |
Stride 0 | 1.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 91.18 |
Vectorization ratio load | 85.71 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 88.89 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 66.67 |
Vectorization ratio other | 91.18 |
Vector-efficiency ratio all | 41.91 |
Vector-efficiency ratio load | 44.64 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 45.83 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 37.50 |
Vector-efficiency ratio other | 37.13 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.04 |
CQA speedup if FP arith vectorized | 1.67 |
CQA speedup if fully vectorized | 2.87 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.50 |
Bottlenecks | micro-operation queue, |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.33 |
CQA cycles if no scalar integer | 31.17 |
CQA cycles if FP arith vectorized | 19.32 |
CQA cycles if fully vectorized | 11.25 |
Front-end cycles | 32.33 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 0.75 |
P1 cycles | 0.75 |
P2 cycles | 0.50 |
P3 cycles | 1.00 |
P4 cycles | 0.67 |
P5 cycles | 0.67 |
P6 cycles | 0.67 |
P7 cycles | 21.50 |
P8 cycles | 21.42 |
P9 cycles | 21.58 |
P10 cycles | 21.50 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 15.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 77.00 |
Nb uops | 194.00 |
Nb loads | 6.00 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.04 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 17.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 9.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 6.93 |
Bytes prefetched | 0.00 |
Bytes loaded | 192.00 |
Bytes stored | 32.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 3.00 |
Vectorization ratio all | 92.54 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 88.89 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 66.67 |
Vectorization ratio other | 91.18 |
Vector-efficiency ratio all | 42.35 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 45.83 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 37.50 |
Vector-efficiency ratio other | 37.13 |
Path / |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 78 |
nb uops | 195 |
loop length | 465 |
used x86 registers | 5.50 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 22 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.80 |
micro-operation queue | 32.50 cycles |
front end | 32.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.25 | 0.75 | 0.75 | 0.50 | 1.25 | 0.83 | 0.83 | 0.83 | 21.50 | 21.42 | 21.58 | 21.50 | 16.00 | 16.00 |
cycles | 1.25 | 0.75 | 0.75 | 0.50 | 1.25 | 0.83 | 0.83 | 0.83 | 21.50 | 21.42 | 21.58 | 21.50 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | 15.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 32.50 |
Dispatch | 21.58 |
DIV/SQRT | 15.00 |
Data deps. | 0.00 |
Overall L1 | 32.50 |
all | 96% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 91% |
all | 88% |
load | 92% |
store | 100% |
mul | 80% |
add-sub | 100% |
fma | 100% |
div/sqrt | 66% |
other | 90% |
all | 91% |
load | 92% |
store | 100% |
mul | 88% |
add-sub | 100% |
fma | 100% |
div/sqrt | 66% |
other | 91% |
all | 39% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 26% |
all | 43% |
load | 47% |
store | 50% |
mul | 42% |
add-sub | 50% |
fma | 50% |
div/sqrt | 37% |
other | 43% |
all | 42% |
load | 47% |
store | 50% |
mul | 45% |
add-sub | 50% |
fma | 50% |
div/sqrt | 37% |
other | 37% |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 79 |
nb uops | 196 |
loop length | 471 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 22 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.80 |
micro-operation queue | 32.67 cycles |
front end | 32.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.75 | 0.75 | 0.50 | 1.50 | 1.00 | 1.00 | 1.00 | 21.50 | 21.42 | 21.58 | 21.50 | 16.00 | 16.00 |
cycles | 1.50 | 0.75 | 0.75 | 0.50 | 1.50 | 1.00 | 1.00 | 1.00 | 21.50 | 21.42 | 21.58 | 21.50 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | 15.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 32.67 |
Dispatch | 21.58 |
DIV/SQRT | 15.00 |
Data deps. | 0.00 |
Overall L1 | 32.67 |
all | 96% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 91% |
all | 87% |
load | 85% |
store | 100% |
mul | 80% |
add-sub | 100% |
fma | 100% |
div/sqrt | 66% |
other | 90% |
all | 91% |
load | 85% |
store | 100% |
mul | 88% |
add-sub | 100% |
fma | 100% |
div/sqrt | 66% |
other | 91% |
all | 39% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 26% |
all | 43% |
load | 44% |
store | 50% |
mul | 42% |
add-sub | 50% |
fma | 50% |
div/sqrt | 37% |
other | 43% |
all | 41% |
load | 44% |
store | 50% |
mul | 45% |
add-sub | 50% |
fma | 50% |
div/sqrt | 37% |
other | 37% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VANDPD %YMM10,%YMM26,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMULLQ %YMM30,%YMM1,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM31,%YMM0,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPADDQ %YMM30,%YMM31,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPXORD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
KXNORW %K0,%K0,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM30,1),%YMM31{%K3} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VDIVPD %YMM31,%YMM7,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VPBLENDMD %XMM23,%XMM22,%XMM30{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VANDPD %YMM10,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VANDPD %YMM10,%YMM28,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VSUBPD %YMM7,%YMM11,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM16,%YMM31,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VDIVSD %XMM29,%XMM12,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VBROADCASTSD %XMM17,%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VCMPPD $0x2,%YMM31,%YMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %YMM8,%YMM31{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMOVSXDQ %XMM30,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM30,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
KMOVQ %K2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
VXORPD %XMM18,%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%R15,%YMM30,8),%YMM18{%K1} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VFMADD213PD %YMM8,%YMM7,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %YMM18,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VFMADD231PD %YMM17,%YMM16,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM14,%XMM29,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM16,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMULPD %YMM8,%YMM16,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPPD $0x2,%YMM31,%YMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %YMM8,%YMM31{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VCMPPD $0x2,%YMM9,%YMM28,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %YMM15,%YMM31,%YMM31{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VMOVAPD %YMM31,%YMM8{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSUBPD %YMM7,%YMM13,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD213PD %YMM27,%YMM8,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM26,%YMM7,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %YMM7,(%R14,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 1 |
ADD $0x4,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R9,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430ab0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3bd0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VMOVUPD (%R13,%RDX,8),%YMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPPD $0x1,%YMM9,%YMM26,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPBLENDMD %XMM23,%XMM25,%XMM8{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %XMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM8,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPBROADCASTQ %RDX,%YMM8 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
VPADDQ %YMM2,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPSUBQ %YMM4,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPSLLQ $0x3,%YMM8,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPMULLQ %YMM30,%YMM6,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM31,%YMM5,%YMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPADDQ %YMM8,%YMM28,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VXORPD %XMM27,%XMM27,%XMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM8,1),%YMM27{%K2} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VPBLENDMD %XMM24,%XMM22,%XMM8{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPBLENDMD %XMM25,%XMM23,%XMM29{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %XMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMULLQ %YMM8,%YMM6,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM8,%YMM28,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM8,1),%YMM7{%K2} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VPMOVSXDQ %XMM29,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMULLQ %YMM8,%YMM6,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM8,%YMM28,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
KXNORW %K0,%K0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM8,1),%YMM28{%K2} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VSUBPD %YMM7,%YMM27,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VSUBPD %YMM27,%YMM28,%YMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM8,%YMM28,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPPD $0x1,%YMM7,%YMM9,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
KORTESTB %K2,%K2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
JE 4308d0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VMOVSD (%R15,%RSI,8),%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
JMP 4308d0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | advec_mom_kernel.f90:81-241 |
Module | exec |
nb instructions | 77 |
nb uops | 194 |
loop length | 459 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 22 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.80 |
micro-operation queue | 32.33 cycles |
front end | 32.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.75 | 0.75 | 0.50 | 1.00 | 0.67 | 0.67 | 0.67 | 21.50 | 21.42 | 21.58 | 21.50 | 16.00 | 16.00 |
cycles | 1.00 | 0.75 | 0.75 | 0.50 | 1.00 | 0.67 | 0.67 | 0.67 | 21.50 | 21.42 | 21.58 | 21.50 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | 15.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 32.33 |
Dispatch | 21.58 |
DIV/SQRT | 15.00 |
Data deps. | 0.00 |
Overall L1 | 32.33 |
all | 96% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 91% |
all | 89% |
load | 100% |
store | 100% |
mul | 80% |
add-sub | 100% |
fma | 100% |
div/sqrt | 66% |
other | 90% |
all | 92% |
load | 100% |
store | 100% |
mul | 88% |
add-sub | 100% |
fma | 100% |
div/sqrt | 66% |
other | 91% |
all | 39% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 26% |
all | 44% |
load | 50% |
store | 50% |
mul | 42% |
add-sub | 50% |
fma | 50% |
div/sqrt | 37% |
other | 43% |
all | 42% |
load | 50% |
store | 50% |
mul | 45% |
add-sub | 50% |
fma | 50% |
div/sqrt | 37% |
other | 37% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VANDPD %YMM10,%YMM26,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMULLQ %YMM30,%YMM1,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM31,%YMM0,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPADDQ %YMM30,%YMM31,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPXORD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
KXNORW %K0,%K0,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM30,1),%YMM31{%K3} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VDIVPD %YMM31,%YMM7,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VPBLENDMD %XMM23,%XMM22,%XMM30{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VANDPD %YMM10,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VANDPD %YMM10,%YMM28,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VSUBPD %YMM7,%YMM11,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM16,%YMM31,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VDIVSD %XMM29,%XMM12,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VBROADCASTSD %XMM17,%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VCMPPD $0x2,%YMM31,%YMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %YMM8,%YMM31{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMOVSXDQ %XMM30,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM30,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
KMOVQ %K2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
VXORPD %XMM18,%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%R15,%YMM30,8),%YMM18{%K1} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VFMADD213PD %YMM8,%YMM7,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %YMM18,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VFMADD231PD %YMM17,%YMM16,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM14,%XMM29,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD %XMM16,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMULPD %YMM8,%YMM16,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPPD $0x2,%YMM31,%YMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %YMM8,%YMM31{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VCMPPD $0x2,%YMM9,%YMM28,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %YMM15,%YMM31,%YMM31{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VMOVAPD %YMM31,%YMM8{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSUBPD %YMM7,%YMM13,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VFMADD213PD %YMM27,%YMM8,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM26,%YMM7,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD %YMM7,(%R14,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 1 |
ADD $0x4,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R9,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430ab0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3bd0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VMOVUPD (%R13,%RDX,8),%YMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPPD $0x1,%YMM9,%YMM26,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPBLENDMD %XMM23,%XMM25,%XMM8{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %XMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM8,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPBROADCASTQ %RDX,%YMM8 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
VPADDQ %YMM2,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPSUBQ %YMM4,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPSLLQ $0x3,%YMM8,%YMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPMULLQ %YMM30,%YMM6,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM31,%YMM5,%YMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPADDQ %YMM8,%YMM28,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VXORPD %XMM27,%XMM27,%XMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM8,1),%YMM27{%K2} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VPBLENDMD %XMM24,%XMM22,%XMM8{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPBLENDMD %XMM25,%XMM23,%XMM29{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %XMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMULLQ %YMM8,%YMM6,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM8,%YMM28,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM8,1),%YMM7{%K2} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VPMOVSXDQ %XMM29,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
VPSUBQ %YMM3,%YMM8,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMULLQ %YMM8,%YMM6,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPADDQ %YMM8,%YMM28,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
KXNORW %K0,%K0,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (,%YMM8,1),%YMM28{%K2} | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 1.42 | 1.42 | 1.42 | 3 | 3 | 0-16 | 4 |
VSUBPD %YMM7,%YMM27,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VSUBPD %YMM27,%YMM28,%YMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM8,%YMM28,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPPD $0x1,%YMM7,%YMM9,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
KORTESTB %K2,%K2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
JE 4308d0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x39f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |