| Loop Id: 168 | Module: exec | Source: advec_cell.cpp:149-150 | Coverage: 1.29% |
|---|
| Loop Id: 168 | Module: exec | Source: advec_cell.cpp:149-150 | Coverage: 1.29% |
|---|
0x428a1a VMOVUPD (%R10,%RAX,1),%ZMM0 [1] |
0x428a21 VADDPD (%R13,%RAX,1),%ZMM0,%ZMM2 [2] |
0x428a29 VSUBPD (%R11,%RAX,1),%ZMM2,%ZMM8 [4] |
0x428a30 VMOVUPD %ZMM8,(%RBX,%RAX,1) [5] |
0x428a37 VMOVUPD (%R10,%RAX,1),%ZMM10 [1] |
0x428a3e VMOVUPD %ZMM10,(%RDX,%RAX,1) [3] |
0x428a45 VMOVUPD 0x40(%R10,%RAX,1),%ZMM12 [1] |
0x428a4d VADDPD 0x40(%R13,%RAX,1),%ZMM12,%ZMM13 [2] |
0x428a55 VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 [4] |
0x428a5d VMOVUPD %ZMM14,0x40(%RBX,%RAX,1) [5] |
0x428a65 VMOVUPD 0x40(%R10,%RAX,1),%ZMM15 [1] |
0x428a6d VMOVUPD %ZMM15,0x40(%RDX,%RAX,1) [3] |
0x428a75 VMOVUPD 0x80(%R10,%RAX,1),%ZMM7 [1] |
0x428a7d VADDPD 0x80(%R13,%RAX,1),%ZMM7,%ZMM9 [2] |
0x428a85 VSUBPD 0x80(%R11,%RAX,1),%ZMM9,%ZMM0 [4] |
0x428a8d VMOVUPD %ZMM0,0x80(%RBX,%RAX,1) [5] |
0x428a95 VMOVUPD 0x80(%R10,%RAX,1),%ZMM2 [1] |
0x428a9d VMOVUPD %ZMM2,0x80(%RDX,%RAX,1) [3] |
0x428aa5 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM8 [1] |
0x428aad VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM10 [2] |
0x428ab5 VSUBPD 0xc0(%R11,%RAX,1),%ZMM10,%ZMM12 [4] |
0x428abd VMOVUPD %ZMM12,0xc0(%RBX,%RAX,1) [5] |
0x428ac5 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM13 [1] |
0x428acd VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) [3] |
0x428ad5 ADD $0x100,%RAX |
0x428adb CMP %RAX,%R14 |
0x428ade JNE 428a1a |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 149 - 150 |
-------------------------------------------------------------------------------- |
149: pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
150: post_vol(i, j) = volume(i, j); |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | P5, P6, P7, |
| Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5 |
| Source | advec_cell.cpp:149-150 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.33 |
| CQA cycles if no scalar integer | 13.33 |
| CQA cycles if FP arith vectorized | 13.33 |
| CQA cycles if fully vectorized | 13.33 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.25 |
| P2 cycles | 0.25 |
| P3 cycles | 0.50 |
| P4 cycles | 13.33 |
| P5 cycles | 13.33 |
| P6 cycles | 13.33 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 8.00 |
| P10 cycles | 8.00 |
| P11 cycles | 8.00 |
| P12 cycles | 8.00 |
| P13 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 27.00 |
| Nb uops | 34.00 |
| Nb loads | 16.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.80 |
| Nb FLOP add-sub | 64.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 115.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1024.00 |
| Bytes stored | 512.00 |
| Stride 0 | 0.00 |
| Stride 1 | 4.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | P5, P6, P7, |
| Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5 |
| Source | advec_cell.cpp:149-150 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.33 |
| CQA cycles if no scalar integer | 13.33 |
| CQA cycles if FP arith vectorized | 13.33 |
| CQA cycles if fully vectorized | 13.33 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.25 |
| P2 cycles | 0.25 |
| P3 cycles | 0.50 |
| P4 cycles | 13.33 |
| P5 cycles | 13.33 |
| P6 cycles | 13.33 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 8.00 |
| P10 cycles | 8.00 |
| P11 cycles | 8.00 |
| P12 cycles | 8.00 |
| P13 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 27.00 |
| Nb uops | 34.00 |
| Nb loads | 16.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.80 |
| Nb FLOP add-sub | 64.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 115.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1024.00 |
| Bytes stored | 512.00 |
| Stride 0 | 0.00 |
| Stride 1 | 4.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5 |
| Source file and lines | advec_cell.cpp:149-150 |
| Module | exec |
| nb instructions | 27 |
| nb uops | 34 |
| loop length | 202 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 10 |
| nb stack references | 0 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 | 4.00 | 4.00 | 8.00 | 8.00 |
| cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 8.00 | 8.00 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.67 |
| Dispatch | 13.33 |
| Data deps. | 1.00 |
| Overall L1 | 13.33 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R10,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD (%R13,%RAX,1),%ZMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD (%R11,%RAX,1),%ZMM2,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM8,(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD (%R10,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM10,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x40(%R10,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD 0x40(%R13,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM14,0x40(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x40(%R10,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM15,0x40(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x80(%R10,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD 0x80(%R13,%RAX,1),%ZMM7,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD 0x80(%R11,%RAX,1),%ZMM9,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM0,0x80(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x80(%R10,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM2,0x80(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0xc0(%R10,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD 0xc0(%R11,%RAX,1),%ZMM10,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM12,0xc0(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0xc0(%R10,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| ADD $0x100,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP %RAX,%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| JNE 428a1a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x24a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
| Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5 |
| Source file and lines | advec_cell.cpp:149-150 |
| Module | exec |
| nb instructions | 27 |
| nb uops | 34 |
| loop length | 202 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 10 |
| nb stack references | 0 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 | 4.00 | 4.00 | 8.00 | 8.00 |
| cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 8.00 | 8.00 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.67 |
| Dispatch | 13.33 |
| Data deps. | 1.00 |
| Overall L1 | 13.33 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R10,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD (%R13,%RAX,1),%ZMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD (%R11,%RAX,1),%ZMM2,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM8,(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD (%R10,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM10,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x40(%R10,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD 0x40(%R13,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM14,0x40(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x40(%R10,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM15,0x40(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x80(%R10,%RAX,1),%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD 0x80(%R13,%RAX,1),%ZMM7,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD 0x80(%R11,%RAX,1),%ZMM9,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM0,0x80(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0x80(%R10,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM2,0x80(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0xc0(%R10,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VSUBPD 0xc0(%R11,%RAX,1),%ZMM10,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM12,0xc0(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| VMOVUPD 0xc0(%R10,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
| ADD $0x100,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP %RAX,%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| JNE 428a1a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x24a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
