| Function: __svml_i64div2 | Module: exec | Source: :0-0 | Coverage: 0.01% |
|---|
| Function: __svml_i64div2 | Module: exec | Source: :0-0 | Coverage: 0.01% |
|---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x478930 ENDBR64 |
0x478934 PUSH %RAX |
0x478935 CALLQ 0x35e85(%RIP) |
0x47893b POP %RAX |
0x47893c RET |
0x47893d NOPL (%RAX) |
| Path / |
| Source file and lines | |
| Module | exec |
| nb instructions | 5 |
| nb uops | 7 |
| loop length | 13 |
| used x86 registers | 1 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 1.17 cycles |
| front end | 1.17 cycles |
| ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 1.17 |
| Dispatch | 1.00 |
| Overall L1 | 1.17 |
| Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENDBR64 | |||||||||||||||||
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CALLQ 0x35e85(%RIP) | 4 | 0.50 | 0 | 0 | 0 | 0.50 | 0.67 | 0.67 | 0.67 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.20 |
| POP %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Source file and lines | |
| Module | exec |
| nb instructions | 5 |
| nb uops | 7 |
| loop length | 13 |
| used x86 registers | 1 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 1.17 cycles |
| front end | 1.17 cycles |
| ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 1.17 |
| Dispatch | 1.00 |
| Overall L1 | 1.17 |
| Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENDBR64 | |||||||||||||||||
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CALLQ 0x35e85(%RIP) | 4 | 0.50 | 0 | 0 | 0 | 0.50 | 0.67 | 0.67 | 0.67 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.20 |
| POP %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ○__svml_i64div2 | 0.01 | 0 |
