Loop Id: 422 | Module: exec | Source: par_indepset.c:65-67 | Coverage: 0.01% |
---|
Loop Id: 422 | Module: exec | Source: par_indepset.c:65-67 | Coverage: 0.01% |
---|
0x42c0f0 VZEROUPPER |
0x42c0f3 CALL 4e8630 <hypre_Rand> |
0x42c0f8 VMOVUPD %XMM0,-0x50(%RBP) [2] |
0x42c0fd CALL 4e8630 <hypre_Rand> |
0x42c102 VMOVUPD %XMM0,-0x40(%RBP) [2] |
0x42c107 CALL 4e8630 <hypre_Rand> |
0x42c10c VMOVUPD %XMM0,-0x30(%RBP) [2] |
0x42c111 CALL 4e8630 <hypre_Rand> |
0x42c116 VMOVUPD -0x50(%RBP),%XMM1 [2] |
0x42c11b VPUNPCKLQDQ -0x40(%RBP),%XMM1,%XMM1 [2] |
0x42c120 VMOVUPD -0x30(%RBP),%XMM2 [2] |
0x42c125 VPUNPCKLQDQ %XMM0,%XMM2,%XMM0 |
0x42c129 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
0x42c12f VADDPD -0x20(%R15),%YMM0,%YMM0 [1] |
0x42c135 VMOVUPD %YMM0,-0x20(%R15) [1] |
0x42c13b VZEROUPPER |
0x42c13e CALL 4e8630 <hypre_Rand> |
0x42c143 VMOVUPD %XMM0,-0x50(%RBP) [2] |
0x42c148 CALL 4e8630 <hypre_Rand> |
0x42c14d VMOVUPD %XMM0,-0x40(%RBP) [2] |
0x42c152 CALL 4e8630 <hypre_Rand> |
0x42c157 VMOVUPD %XMM0,-0x30(%RBP) [2] |
0x42c15c CALL 4e8630 <hypre_Rand> |
0x42c161 VMOVUPD -0x50(%RBP),%XMM1 [2] |
0x42c166 VPUNPCKLQDQ -0x40(%RBP),%XMM1,%XMM1 [2] |
0x42c16b VMOVUPD -0x30(%RBP),%XMM2 [2] |
0x42c170 VPUNPCKLQDQ %XMM0,%XMM2,%XMM0 |
0x42c174 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
0x42c17a VADDPD (%R15),%YMM0,%YMM0 [1] |
0x42c17f VMOVUPD %YMM0,(%R15) [1] |
0x42c184 ADD $0x40,%R15 |
0x42c188 DEC %R14 |
0x42c18b JNE 42c0f0 |
/scratch_na/users/xoserete/qaas_runs/171-587-0261/intel/AMG/build/AMG/AMG/parcsr_ls/par_indepset.c: 65 - 67 |
-------------------------------------------------------------------------------- |
65: for (i = 0; i < S_num_nodes; i++) |
66: { |
67: measure_array[i] += hypre_Rand(); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►96.97+ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2176 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.28.so | |
►3.03+ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2176 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:638 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.28.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.22 |
CQA speedup if fully vectorized | 4.47 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.25 |
Bottlenecks | |
Function | hypre_BoomerAMGIndepSetInit |
Source | par_indepset.c:65-67 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 18.00 |
CQA cycles if no scalar integer | 18.00 |
CQA cycles if FP arith vectorized | 14.73 |
CQA cycles if fully vectorized | 4.02 |
Front-end cycles | 7.00 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 4.00 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 8.00 |
P4 cycles | 4.00 |
P5 cycles | 0.50 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.00 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 18 |
FE+BE cycles (UFS) | 14.15 |
Stall cycles (UFS) | 8.06 |
Nb insns | 33.00 |
Nb uops | 42.00 |
Nb loads | 8.00 |
Nb stores | 8.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.44 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.78 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 160.00 |
Stride 0 | 1.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 81.82 |
Vectorization ratio load | 75.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 50.00 |
Vector-efficiency ratio all | 27.27 |
Vector-efficiency ratio load | 28.13 |
Vector-efficiency ratio store | 31.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 18.75 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.22 |
CQA speedup if fully vectorized | 4.47 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.25 |
Bottlenecks | |
Function | hypre_BoomerAMGIndepSetInit |
Source | par_indepset.c:65-67 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 18.00 |
CQA cycles if no scalar integer | 18.00 |
CQA cycles if FP arith vectorized | 14.73 |
CQA cycles if fully vectorized | 4.02 |
Front-end cycles | 7.00 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 4.00 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 8.00 |
P4 cycles | 4.00 |
P5 cycles | 0.50 |
P6 cycles | 8.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 0.00 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 18 |
FE+BE cycles (UFS) | 14.15 |
Stall cycles (UFS) | 8.06 |
Nb insns | 33.00 |
Nb uops | 42.00 |
Nb loads | 8.00 |
Nb stores | 8.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.44 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.78 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 160.00 |
Stride 0 | 1.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 81.82 |
Vectorization ratio load | 75.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 50.00 |
Vector-efficiency ratio all | 27.27 |
Vector-efficiency ratio load | 28.13 |
Vector-efficiency ratio store | 31.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 18.75 |
Path / |
Function | hypre_BoomerAMGIndepSetInit |
Source file and lines | par_indepset.c:65-67 |
Module | exec |
nb instructions | 33 |
nb uops | 42 |
loop length | 161 |
used x86 registers | 3 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 7.00 cycles |
front end | 7.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 4.00 | 2.67 | 2.67 | 8.00 | 4.00 | 0.50 | 8.00 | 8.00 | 8.00 | 0.00 | 2.67 |
cycles | 0.50 | 4.00 | 2.67 | 2.67 | 8.00 | 4.00 | 0.50 | 8.00 | 8.00 | 8.00 | 0.00 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 18.00 |
FE+BE cycles | 14.15 |
Stall cycles | 8.06 |
RS full (events) | 5.91 |
SB full (events) | 5.85 |
Front-end | 7.00 |
Dispatch | 8.00 |
Data deps. | 18.00 |
Overall L1 | 18.00 |
all | 33% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 33% |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 81% |
load | 75% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 16% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 16% |
all | 31% |
load | 33% |
store | 31% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 27% |
load | 28% |
store | 31% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD -0x50(%RBP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ -0x40(%RBP),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
VMOVUPD -0x30(%RBP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ %XMM0,%XMM2,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD -0x20(%R15),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVUPD %YMM0,-0x20(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD -0x50(%RBP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ -0x40(%RBP),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
VMOVUPD -0x30(%RBP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ %XMM0,%XMM2,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R15),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVUPD %YMM0,(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x40,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 42c0f0 <hypre_BoomerAMGIndepSetInit+0xd0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_BoomerAMGIndepSetInit |
Source file and lines | par_indepset.c:65-67 |
Module | exec |
nb instructions | 33 |
nb uops | 42 |
loop length | 161 |
used x86 registers | 3 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 3 |
micro-operation queue | 7.00 cycles |
front end | 7.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 4.00 | 2.67 | 2.67 | 8.00 | 4.00 | 0.50 | 8.00 | 8.00 | 8.00 | 0.00 | 2.67 |
cycles | 0.50 | 4.00 | 2.67 | 2.67 | 8.00 | 4.00 | 0.50 | 8.00 | 8.00 | 8.00 | 0.00 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 18.00 |
FE+BE cycles | 14.15 |
Stall cycles | 8.06 |
RS full (events) | 5.91 |
SB full (events) | 5.85 |
Front-end | 7.00 |
Dispatch | 8.00 |
Data deps. | 18.00 |
Overall L1 | 18.00 |
all | 33% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 33% |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 81% |
load | 75% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 16% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 16% |
all | 31% |
load | 33% |
store | 31% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 27% |
load | 28% |
store | 31% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD -0x50(%RBP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ -0x40(%RBP),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
VMOVUPD -0x30(%RBP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ %XMM0,%XMM2,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD -0x20(%R15),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVUPD %YMM0,-0x20(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD %XMM0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CALL 4e8630 <hypre_Rand> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVUPD -0x50(%RBP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ -0x40(%RBP),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
VMOVUPD -0x30(%RBP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPUNPCKLQDQ %XMM0,%XMM2,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%R15),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVUPD %YMM0,(%R15) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x40,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 42c0f0 <hypre_BoomerAMGIndepSetInit+0xd0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |