Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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/scratch_na/users/xoserete/qaas_runs/171-587-0261/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2311 - 2320 |
-------------------------------------------------------------------------------- |
2311: for (i=0; i < num_var; i++) |
2312: { |
2313: if (CF_marker[i] > 0 ) |
2314: { |
2315: if (CF_marker[i] == 1) CF_marker[i] = new_CF_marker[cnt++]; |
2316: else { CF_marker[i] = 1; cnt++;} |
2317: } |
2318: } |
2319: |
2320: return 0; |
0x48cc80 TEST %RSI,%RSI |
0x48cc83 JLE 48cd61 |
0x48cc89 CMP $0x4,%RSI |
0x48cc8d JAE 48cca6 |
0x48cc8f XOR %EAX,%EAX |
0x48cc91 MOV %RSI,%RCX |
0x48cc94 AND $-0x4,%RCX |
0x48cc98 CMP %RSI,%RCX |
0x48cc9b JNE 48cd7f |
0x48cca1 JMP 48cd61 |
0x48cca6 PUSH %RBP |
0x48cca7 MOV %RSP,%RBP |
0x48ccaa MOV %RSI,%RCX |
0x48ccad SHR $0x2,%RCX |
0x48ccb1 LEA 0x18(%RDI),%R8 |
0x48ccb5 XOR %EAX,%EAX |
0x48ccb7 JMP 48ccd3 |
0x48ccb9 NOPL (%RAX) |
(2446) 0x48ccc0 INC %RAX |
(2446) 0x48ccc3 MOV %R9,(%R8) |
(2446) 0x48ccc6 ADD $0x20,%R8 |
(2446) 0x48ccca DEC %RCX |
(2446) 0x48cccd JE 48cd54 |
(2446) 0x48ccd3 MOV -0x18(%R8),%R10 |
(2446) 0x48ccd7 TEST %R10,%R10 |
(2446) 0x48ccda JLE 48ccf3 |
(2446) 0x48ccdc MOV $0x1,%R9D |
(2446) 0x48cce2 CMP $0x1,%R10 |
(2446) 0x48cce6 JNE 48ccec |
(2446) 0x48cce8 MOV (%RDX,%RAX,8),%R9 |
(2446) 0x48ccec INC %RAX |
(2446) 0x48ccef MOV %R9,-0x18(%R8) |
(2446) 0x48ccf3 MOV -0x10(%R8),%R10 |
(2446) 0x48ccf7 TEST %R10,%R10 |
(2446) 0x48ccfa JLE 48cd13 |
(2446) 0x48ccfc MOV $0x1,%R9D |
(2446) 0x48cd02 CMP $0x1,%R10 |
(2446) 0x48cd06 JNE 48cd0c |
(2446) 0x48cd08 MOV (%RDX,%RAX,8),%R9 |
(2446) 0x48cd0c INC %RAX |
(2446) 0x48cd0f MOV %R9,-0x10(%R8) |
(2446) 0x48cd13 MOV -0x8(%R8),%R10 |
(2446) 0x48cd17 TEST %R10,%R10 |
(2446) 0x48cd1a JLE 48cd33 |
(2446) 0x48cd1c MOV $0x1,%R9D |
(2446) 0x48cd22 CMP $0x1,%R10 |
(2446) 0x48cd26 JNE 48cd2c |
(2446) 0x48cd28 MOV (%RDX,%RAX,8),%R9 |
(2446) 0x48cd2c INC %RAX |
(2446) 0x48cd2f MOV %R9,-0x8(%R8) |
(2446) 0x48cd33 MOV (%R8),%R10 |
(2446) 0x48cd36 TEST %R10,%R10 |
(2446) 0x48cd39 JLE 48ccc6 |
(2446) 0x48cd3b MOV $0x1,%R9D |
(2446) 0x48cd41 CMP $0x1,%R10 |
(2446) 0x48cd45 JNE 48ccc0 |
(2446) 0x48cd4b MOV (%RDX,%RAX,8),%R9 |
(2446) 0x48cd4f JMP 48ccc0 |
0x48cd54 POP %RBP |
0x48cd55 MOV %RSI,%RCX |
0x48cd58 AND $-0x4,%RCX |
0x48cd5c CMP %RSI,%RCX |
0x48cd5f JNE 48cd7f |
0x48cd61 XOR %EAX,%EAX |
0x48cd63 RET |
0x48cd64 NOPW %CS:(%RAX,%RAX,1) |
(2445) 0x48cd70 INC %RAX |
(2445) 0x48cd73 MOV %R8,(%RDI,%RCX,8) |
(2445) 0x48cd77 INC %RCX |
(2445) 0x48cd7a CMP %RCX,%RSI |
(2445) 0x48cd7d JE 48cd61 |
(2445) 0x48cd7f MOV (%RDI,%RCX,8),%R9 |
(2445) 0x48cd83 TEST %R9,%R9 |
(2445) 0x48cd86 JLE 48cd77 |
(2445) 0x48cd88 MOV $0x1,%R8D |
(2445) 0x48cd8e CMP $0x1,%R9 |
(2445) 0x48cd92 JNE 48cd70 |
(2445) 0x48cd94 MOV (%RDX,%RAX,8),%R8 |
(2445) 0x48cd98 JMP 48cd70 |
0x48cd9a NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_BoomerAMGSetup | par_amg_setup.c:730 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.28.so |
Path / |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 98 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
cycles | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.59 |
Stall cycles | 0.00 |
Front-end | 4.50 |
Dispatch | 3.00 |
Overall L1 | 4.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 48cd61 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 48cca6 <hypre_BoomerAMGCorrectCFMarker+0x26> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 48cd7f <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 48cd61 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 48ccd3 <hypre_BoomerAMGCorrectCFMarker+0x53> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 48cd7f <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 98 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
cycles | 3.00 | 2.00 | 0.67 | 0.67 | 0.50 | 2.00 | 3.00 | 0.50 | 0.50 | 0.50 | 2.00 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.59 |
Stall cycles | 0.00 |
Front-end | 4.50 |
Dispatch | 3.00 |
Overall L1 | 4.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 48cd61 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 48cca6 <hypre_BoomerAMGCorrectCFMarker+0x26> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 48cd7f <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 48cd61 <hypre_BoomerAMGCorrectCFMarker+0xe1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 48ccd3 <hypre_BoomerAMGCorrectCFMarker+0x53> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 48cd7f <hypre_BoomerAMGCorrectCFMarker+0xff> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGCorrectCFMarker– | 0.01 | 0 |
○Loop 2446 - par_strength.c:2311-2315 - exec | 0.01 | 0.11 |
○Loop 2445 - par_strength.c:2311-2315 - exec | 0 | 0 |