Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.49% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.49% |
---|
/scratch_na/users/xoserete/qaas_runs/171-587-0261/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1584: tmp_marker = NULL; |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
1600: { thread_stop = pass_pointer[1] + pass_length; } |
1601: else |
1602: { thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); } |
1603: |
1604: /* determine P for points of pass 1, i.e. neighbors of coarse points */ |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x474420 PUSH %RBP |
0x474421 MOV %RSP,%RBP |
0x474424 PUSH %R15 |
0x474426 PUSH %R14 |
0x474428 PUSH %R13 |
0x47442a PUSH %R12 |
0x47442c PUSH %RBX |
0x47442d AND $-0x40,%RSP |
0x474431 SUB $0x100,%RSP |
0x474438 MOV 0xf8(%RDI),%RAX |
0x47443f MOV 0xf0(%RDI),%RDX |
0x474446 MOV 0xe0(%RDI),%RCX |
0x47444d MOV 0xd8(%RDI),%RSI |
0x474454 MOV 0xd0(%RDI),%R8 |
0x47445b MOV 0xc8(%RDI),%R9 |
0x474462 MOV %RAX,0xf8(%RSP) |
0x47446a MOV 0xc0(%RDI),%R10 |
0x474471 MOV 0xb0(%RDI),%R12 |
0x474478 MOV %RDX,0x98(%RSP) |
0x474480 MOV 0xa8(%RDI),%R13 |
0x474487 MOV 0x90(%RDI),%RAX |
0x47448e MOV %RCX,0x8(%RSP) |
0x474493 MOV 0xb8(%RDI),%R11 |
0x47449a MOV 0xe8(%RDI),%RBX |
0x4744a1 MOV %RSI,0x90(%RSP) |
0x4744a9 MOV %R8,0x28(%RSP) |
0x4744ae MOV 0xa0(%RDI),%R14 |
0x4744b5 MOV %R9,0x20(%RSP) |
0x4744ba MOV 0x98(%RDI),%R15 |
0x4744c1 MOV %R10,0x60(%RSP) |
0x4744c6 MOV %R12,0xc8(%RSP) |
0x4744ce MOV %R13,0x70(%RSP) |
0x4744d3 MOV %RAX,0xb0(%RSP) |
0x4744db MOV %R11,0x58(%RSP) |
0x4744e0 MOV 0x88(%RDI),%R11 |
0x4744e7 MOV 0x80(%RDI),%RDX |
0x4744ee MOV 0x78(%RDI),%RCX |
0x4744f2 MOV 0x70(%RDI),%RSI |
0x4744f6 MOV 0x68(%RDI),%R8 |
0x4744fa MOV 0x60(%RDI),%R9 |
0x4744fe MOV 0x58(%RDI),%R10 |
0x474502 MOV %RDX,0x88(%RSP) |
0x47450a MOV 0x40(%RDI),%RAX |
0x47450e MOV 0x38(%RDI),%RDX |
0x474512 MOV %RCX,0x50(%RSP) |
0x474517 MOV 0x50(%RDI),%R12 |
0x47451b MOV 0x28(%RDI),%RCX |
0x47451f MOV %RSI,0xd8(%RSP) |
0x474527 MOV 0x48(%RDI),%R13 |
0x47452b MOV 0x20(%RDI),%RSI |
0x47452f MOV %R8,0x80(%RSP) |
0x474537 MOV %R9,0x48(%RSP) |
0x47453c MOV 0x18(%RDI),%R8 |
0x474540 MOV 0x10(%RDI),%R9 |
0x474544 MOV %R10,0xd0(%RSP) |
0x47454c MOV %RAX,0x40(%RSP) |
0x474551 MOV 0x30(%RDI),%R10 |
0x474555 MOV 0x8(%RDI),%RAX |
0x474559 MOV (%RDI),%RDI |
0x47455c MOV %RDX,0xe0(%RSP) |
0x474564 MOV %RCX,0x38(%RSP) |
0x474569 MOV %RSI,0xf0(%RSP) |
0x474571 MOV %R8,0x18(%RSP) |
0x474576 MOV %R9,0xc0(%RSP) |
0x47457e MOV %RAX,0xe8(%RSP) |
0x474586 MOV %RDI,0x10(%RSP) |
0x47458b TEST %RBX,%RBX |
0x47458e JNE 4751ef |
0x474594 TEST %R12,%R12 |
0x474597 JNE 475360 |
0x47459d XOR %EBX,%EBX |
0x47459f XOR %R12D,%R12D |
0x4745a2 MOV %R10,0x78(%RSP) |
0x4745a7 MOV %R11,0xa0(%RSP) |
0x4745af VMOVSD %XMM1,0xa8(%RSP) |
0x4745b8 CALL 5b39c0 <hypre_GetThreadNum> |
0x4745bd MOV %RAX,0xb8(%RSP) |
0x4745c5 CALL 5b39b0 <hypre_NumActiveThreads> |
0x4745ca MOV 0xb8(%RSP),%R11 |
0x4745d2 MOV 0xc8(%RSP),%R8 |
0x4745da MOV %RAX,%RSI |
0x4745dd MOV 0xf8(%RSP),%RAX |
0x4745e5 VMOVSD 0xa8(%RSP),%XMM11 |
0x4745ee MOV %R11,%RCX |
0x4745f1 MOV 0x8(%R8),%R9 |
0x4745f5 MOV 0x78(%RSP),%R10 |
0x4745fa CQTO |
0x4745fc MOV 0xa0(%RSP),%R8 |
0x474604 IDIV %RSI |
0x474607 DEC %RSI |
0x47460a IMUL %RAX,%RCX |
0x47460e ADD %RCX,%RAX |
0x474611 LEA (%R9,%RCX,1),%RDI |
0x474615 MOV 0xf8(%RSP),%RCX |
0x47461d ADD %R9,%RAX |
0x474620 ADD %R9,%RCX |
0x474623 CMP %RSI,%R11 |
0x474626 CMOVNE %RAX,%RCX |
0x47462a CMP %RDI,%RCX |
0x47462d JLE 474fe0 |
0x474633 MOV 0x70(%RSP),%R9 |
0x474638 VMOVQ 0x145800(%RIP),%XMM5 |
0x474640 MOV %R10,%R11 |
0x474643 VXORPD %XMM4,%XMM4,%XMM4 |
0x474647 MOV %R8,%R10 |
0x47464a LEA (%R9,%RDI,8),%RSI |
0x47464e LEA (%R9,%RCX,8),%RAX |
0x474652 MOV %RSI,0xc8(%RSP) |
0x47465a MOV %RAX,0x30(%RSP) |
0x47465f NOP |
(659) 0x474660 MOV 0xc8(%RSP),%RDX |
(659) 0x474668 MOV 0x58(%RSP),%RDI |
(659) 0x47466d MOV (%RDX),%RDX |
(659) 0x474670 MOV (%RDI,%RDX,8),%RCX |
(659) 0x474674 MOV 0x48(%RSP),%RDI |
(659) 0x474679 LEA (,%RDX,8),%R8 |
(659) 0x474681 LEA 0x8(%R8),%R9 |
(659) 0x474685 LEA (%RDI,%R8,1),%RSI |
(659) 0x474689 MOV 0x8(%RDI,%R8,1),%RAX |
(659) 0x47468e MOV %RSI,0xa8(%RSP) |
(659) 0x474696 MOV (%RSI),%RSI |
(659) 0x474699 ADD %RCX,%RAX |
(659) 0x47469c SUB %RSI,%RAX |
(659) 0x47469f MOV %RSI,0xf8(%RSP) |
(659) 0x4746a7 CMP %RAX,%RCX |
(659) 0x4746aa JGE 4747e8 |
(659) 0x4746b0 MOV 0x20(%RSP),%RDI |
(659) 0x4746b5 MOV 0x8(%RDI),%RSI |
(659) 0x4746b9 LEA (%RSI,%RAX,8),%RDI |
(659) 0x4746bd LEA (%RSI,%RCX,8),%RCX |
(659) 0x4746c1 MOV %RDI,%RAX |
(659) 0x4746c4 SUB %RCX,%RAX |
(659) 0x4746c7 SUB $0x8,%RAX |
(659) 0x4746cb SHR $0x3,%RAX |
(659) 0x4746cf INC %RAX |
(659) 0x4746d2 AND $0x7,%EAX |
(659) 0x4746d5 JE 47476d |
(659) 0x4746db CMP $0x1,%RAX |
(659) 0x4746df JE 474759 |
(659) 0x4746e1 CMP $0x2,%RAX |
(659) 0x4746e5 JE 47474a |
(659) 0x4746e7 CMP $0x3,%RAX |
(659) 0x4746eb JE 47473b |
(659) 0x4746ed CMP $0x4,%RAX |
(659) 0x4746f1 JE 47472c |
(659) 0x4746f3 CMP $0x5,%RAX |
(659) 0x4746f7 JE 47471d |
(659) 0x4746f9 CMP $0x6,%RAX |
(659) 0x4746fd JE 47470e |
(659) 0x4746ff MOV (%RCX),%RSI |
(659) 0x474702 ADD $0x8,%RCX |
(659) 0x474706 MOV (%R15,%RSI,8),%RAX |
(659) 0x47470a MOV %RDX,(%R12,%RAX,8) |
(659) 0x47470e MOV (%RCX),%RSI |
(659) 0x474711 ADD $0x8,%RCX |
(659) 0x474715 MOV (%R15,%RSI,8),%RAX |
(659) 0x474719 MOV %RDX,(%R12,%RAX,8) |
(659) 0x47471d MOV (%RCX),%RSI |
(659) 0x474720 ADD $0x8,%RCX |
(659) 0x474724 MOV (%R15,%RSI,8),%RAX |
(659) 0x474728 MOV %RDX,(%R12,%RAX,8) |
(659) 0x47472c MOV (%RCX),%RSI |
(659) 0x47472f ADD $0x8,%RCX |
(659) 0x474733 MOV (%R15,%RSI,8),%RAX |
(659) 0x474737 MOV %RDX,(%R12,%RAX,8) |
(659) 0x47473b MOV (%RCX),%RSI |
(659) 0x47473e ADD $0x8,%RCX |
(659) 0x474742 MOV (%R15,%RSI,8),%RAX |
(659) 0x474746 MOV %RDX,(%R12,%RAX,8) |
(659) 0x47474a MOV (%RCX),%RSI |
(659) 0x47474d ADD $0x8,%RCX |
(659) 0x474751 MOV (%R15,%RSI,8),%RAX |
(659) 0x474755 MOV %RDX,(%R12,%RAX,8) |
(659) 0x474759 MOV (%RCX),%RSI |
(659) 0x47475c ADD $0x8,%RCX |
(659) 0x474760 MOV (%R15,%RSI,8),%RAX |
(659) 0x474764 MOV %RDX,(%R12,%RAX,8) |
(659) 0x474768 CMP %RDI,%RCX |
(659) 0x47476b JE 4747d5 |
(668) 0x47476d MOV (%RCX),%RSI |
(668) 0x474770 ADD $0x40,%RCX |
(668) 0x474774 MOV (%R15,%RSI,8),%RAX |
(668) 0x474778 MOV %RDX,(%R12,%RAX,8) |
(668) 0x47477c MOV -0x38(%RCX),%RSI |
(668) 0x474780 MOV (%R15,%RSI,8),%RAX |
(668) 0x474784 MOV %RDX,(%R12,%RAX,8) |
(668) 0x474788 MOV -0x30(%RCX),%RSI |
(668) 0x47478c MOV (%R15,%RSI,8),%RAX |
(668) 0x474790 MOV %RDX,(%R12,%RAX,8) |
(668) 0x474794 MOV -0x28(%RCX),%RSI |
(668) 0x474798 MOV (%R15,%RSI,8),%RAX |
(668) 0x47479c MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747a0 MOV -0x20(%RCX),%RSI |
(668) 0x4747a4 MOV (%R15,%RSI,8),%RAX |
(668) 0x4747a8 MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747ac MOV -0x18(%RCX),%RSI |
(668) 0x4747b0 MOV (%R15,%RSI,8),%RAX |
(668) 0x4747b4 MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747b8 MOV -0x10(%RCX),%RSI |
(668) 0x4747bc MOV (%R15,%RSI,8),%RAX |
(668) 0x4747c0 MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747c4 MOV -0x8(%RCX),%RSI |
(668) 0x4747c8 MOV (%R15,%RSI,8),%RAX |
(668) 0x4747cc MOV %RDX,(%R12,%RAX,8) |
(668) 0x4747d0 CMP %RDI,%RCX |
(668) 0x4747d3 JNE 47476d |
(659) 0x4747d5 MOV 0xa8(%RSP),%RCX |
(659) 0x4747dd MOV (%RCX),%RDI |
(659) 0x4747e0 MOV %RDI,0xf8(%RSP) |
(659) 0x4747e8 MOV 0x38(%RSP),%RSI |
(659) 0x4747ed VXORPD %XMM0,%XMM0,%XMM0 |
(659) 0x4747f1 VMOVSD %XMM0,%XMM0,%XMM2 |
(659) 0x4747f5 LEA (%RSI,%R8,1),%RAX |
(659) 0x4747f9 LEA (%RSI,%R9,1),%RSI |
(659) 0x4747fd MOV %RAX,0xa0(%RSP) |
(659) 0x474805 MOV (%RAX),%RAX |
(659) 0x474808 MOV %RAX,0xb8(%RSP) |
(659) 0x474810 INC %RAX |
(659) 0x474813 CMP (%RSI),%RAX |
(659) 0x474816 JGE 4748fc |
(659) 0x47481c CMPQ $0x1,0xe8(%RSP) |
(659) 0x474825 JE 475000 |
(659) 0x47482b MOV %R13,0x70(%RSP) |
(659) 0x474830 MOV %RBX,0xb8(%RSP) |
(659) 0x474838 MOV 0xf8(%RSP),%RBX |
(659) 0x474840 MOV %R10,0x78(%RSP) |
(659) 0x474845 MOV 0x10(%RSP),%R10 |
(659) 0x47484a MOV %R9,0x68(%RSP) |
(659) 0x47484f MOV 0xc0(%RSP),%R9 |
(659) 0x474857 NOPW (%RAX,%RAX,1) |
(667) 0x474860 MOV (%R11,%RAX,8),%RCX |
(667) 0x474864 CMPQ $-0x3,(%R10,%RCX,8) |
(667) 0x474869 JE 474882 |
(667) 0x47486b MOV (%R9,%RCX,8),%R13 |
(667) 0x47486f CMP %R13,(%R9,%R8,1) |
(667) 0x474873 JNE 474882 |
(667) 0x474875 MOV 0xf0(%RSP),%RDI |
(667) 0x47487d VADDSD (%RDI,%RAX,8),%XMM0,%XMM0 |
(667) 0x474882 CMP $-0x1,%RCX |
(667) 0x474886 JE 4748d5 |
(667) 0x474888 CMP (%R12,%RCX,8),%RDX |
(667) 0x47488c JNE 4748d5 |
(667) 0x47488e MOV 0xf0(%RSP),%R13 |
(667) 0x474896 LEA (,%RBX,8),%RDI |
(667) 0x47489e VMOVSD (%R13,%RAX,8),%XMM6 |
(667) 0x4748a5 MOV 0xd0(%RSP),%R13 |
(667) 0x4748ad VMOVSD %XMM6,(%R13,%RBX,8) |
(667) 0x4748b4 MOV 0x98(%RSP),%R13 |
(667) 0x4748bc VADDSD %XMM6,%XMM2,%XMM2 |
(667) 0x4748c0 INC %RBX |
(667) 0x4748c3 MOV (%R13,%RCX,8),%RCX |
(667) 0x4748c8 MOV 0x80(%RSP),%R13 |
(667) 0x4748d0 MOV %RCX,(%R13,%RDI,1) |
(667) 0x4748d5 INC %RAX |
(667) 0x4748d8 CMP (%RSI),%RAX |
(667) 0x4748db JL 474860 |
(659) 0x4748dd MOV 0x78(%RSP),%R10 |
(659) 0x4748e2 MOV 0x70(%RSP),%R13 |
(659) 0x4748e7 MOV %RBX,0xf8(%RSP) |
(659) 0x4748ef MOV 0x68(%RSP),%R9 |
(659) 0x4748f4 MOV 0xb8(%RSP),%RBX |
(659) 0x4748fc MOV 0x60(%RSP),%RAX |
(659) 0x474901 MOV 0x50(%RSP),%RDI |
(659) 0x474906 MOV (%RAX,%RDX,8),%RCX |
(659) 0x47490a LEA (%RDI,%R8,1),%RSI |
(659) 0x47490e MOV 0x8(%RDI,%R8,1),%RAX |
(659) 0x474913 MOV %RSI,0xb8(%RSP) |
(659) 0x47491b MOV (%RSI),%RSI |
(659) 0x47491e ADD %RCX,%RAX |
(659) 0x474921 SUB %RSI,%RAX |
(659) 0x474924 CMP %RAX,%RCX |
(659) 0x474927 JGE 474a6d |
(659) 0x47492d MOV 0x28(%RSP),%RDI |
(659) 0x474932 MOV 0x8(%RDI),%RSI |
(659) 0x474936 LEA (%RSI,%RCX,8),%RCX |
(659) 0x47493a LEA (%RSI,%RAX,8),%RSI |
(659) 0x47493e MOV %RSI,%RAX |
(659) 0x474941 SUB %RCX,%RAX |
(659) 0x474944 SUB $0x8,%RAX |
(659) 0x474948 SHR $0x3,%RAX |
(659) 0x47494c INC %RAX |
(659) 0x47494f AND $0x7,%EAX |
(659) 0x474952 JE 4749ea |
(659) 0x474958 CMP $0x1,%RAX |
(659) 0x47495c JE 4749d6 |
(659) 0x47495e CMP $0x2,%RAX |
(659) 0x474962 JE 4749c7 |
(659) 0x474964 CMP $0x3,%RAX |
(659) 0x474968 JE 4749b8 |
(659) 0x47496a CMP $0x4,%RAX |
(659) 0x47496e JE 4749a9 |
(659) 0x474970 CMP $0x5,%RAX |
(659) 0x474974 JE 47499a |
(659) 0x474976 CMP $0x6,%RAX |
(659) 0x47497a JE 47498b |
(659) 0x47497c MOV (%RCX),%RDI |
(659) 0x47497f ADD $0x8,%RCX |
(659) 0x474983 MOV (%R14,%RDI,8),%RAX |
(659) 0x474987 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x47498b MOV (%RCX),%RDI |
(659) 0x47498e ADD $0x8,%RCX |
(659) 0x474992 MOV (%R14,%RDI,8),%RAX |
(659) 0x474996 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x47499a MOV (%RCX),%RDI |
(659) 0x47499d ADD $0x8,%RCX |
(659) 0x4749a1 MOV (%R14,%RDI,8),%RAX |
(659) 0x4749a5 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x4749a9 MOV (%RCX),%RDI |
(659) 0x4749ac ADD $0x8,%RCX |
(659) 0x4749b0 MOV (%R14,%RDI,8),%RAX |
(659) 0x4749b4 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x4749b8 MOV (%RCX),%RDI |
(659) 0x4749bb ADD $0x8,%RCX |
(659) 0x4749bf MOV (%R14,%RDI,8),%RAX |
(659) 0x4749c3 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x4749c7 MOV (%RCX),%RDI |
(659) 0x4749ca ADD $0x8,%RCX |
(659) 0x4749ce MOV (%R14,%RDI,8),%RAX |
(659) 0x4749d2 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x4749d6 MOV (%RCX),%RDI |
(659) 0x4749d9 ADD $0x8,%RCX |
(659) 0x4749dd MOV (%R14,%RDI,8),%RAX |
(659) 0x4749e1 MOV %RDX,(%RBX,%RAX,8) |
(659) 0x4749e5 CMP %RCX,%RSI |
(659) 0x4749e8 JE 474a62 |
(659) 0x4749ea MOV 0xb8(%RSP),%RDI |
(665) 0x4749f2 MOV (%RCX),%RAX |
(665) 0x4749f5 ADD $0x40,%RCX |
(665) 0x4749f9 MOV (%R14,%RAX,8),%RAX |
(665) 0x4749fd MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a01 MOV -0x38(%RCX),%RAX |
(665) 0x474a05 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a09 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a0d MOV -0x30(%RCX),%RAX |
(665) 0x474a11 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a15 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a19 MOV -0x28(%RCX),%RAX |
(665) 0x474a1d MOV (%R14,%RAX,8),%RAX |
(665) 0x474a21 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a25 MOV -0x20(%RCX),%RAX |
(665) 0x474a29 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a2d MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a31 MOV -0x18(%RCX),%RAX |
(665) 0x474a35 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a39 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a3d MOV -0x10(%RCX),%RAX |
(665) 0x474a41 MOV (%R14,%RAX,8),%RAX |
(665) 0x474a45 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a49 MOV -0x8(%RCX),%RAX |
(665) 0x474a4d MOV (%R14,%RAX,8),%RAX |
(665) 0x474a51 MOV %RDX,(%RBX,%RAX,8) |
(665) 0x474a55 CMP %RCX,%RSI |
(665) 0x474a58 JNE 4749f2 |
(659) 0x474a5a MOV %RDI,0xb8(%RSP) |
(659) 0x474a62 MOV 0xb8(%RSP),%RCX |
(659) 0x474a6a MOV (%RCX),%RSI |
(659) 0x474a6d MOV 0x40(%RSP),%RDI |
(659) 0x474a72 MOV (%RDI,%RDX,8),%RAX |
(659) 0x474a76 ADD %RDI,%R9 |
(659) 0x474a79 CMP %RAX,(%R9) |
(659) 0x474a7c JLE 4751d8 |
(659) 0x474a82 CMPQ $0,0x18(%RSP) |
(659) 0x474a88 JE 4750b0 |
(659) 0x474a8e MOV %R12,0x78(%RSP) |
(659) 0x474a93 MOV 0x8(%RSP),%RDI |
(659) 0x474a98 MOV %R11,0x70(%RSP) |
(659) 0x474a9d JMP 474b11 |
0x474a9f NOP |
(664) 0x474aa0 MOV 0xb0(%RSP),%R11 |
(664) 0x474aa8 MOV 0xc0(%RSP),%R12 |
(664) 0x474ab0 MOV (%R11,%RCX,8),%R11 |
(664) 0x474ab4 CMP %R11,(%R12,%R8,1) |
(664) 0x474ab8 JE 474b30 |
(664) 0x474aba CMP $-0x1,%RCX |
(664) 0x474abe JE 474b09 |
(664) 0x474ac0 CMP (%RBX,%RCX,8),%RDX |
(664) 0x474ac4 JNE 474b09 |
(664) 0x474ac6 MOV 0xe0(%RSP),%R11 |
(664) 0x474ace LEA (,%RSI,8),%R12 |
(664) 0x474ad6 VMOVSD (%R11,%RAX,8),%XMM7 |
(664) 0x474adc MOV 0xd8(%RSP),%R11 |
(664) 0x474ae4 VMOVSD %XMM7,(%R11,%RSI,8) |
(664) 0x474aea MOV 0x90(%RSP),%R11 |
(664) 0x474af2 VADDSD %XMM7,%XMM2,%XMM2 |
(664) 0x474af6 INC %RSI |
(664) 0x474af9 MOV (%R11,%RCX,8),%RCX |
(664) 0x474afd MOV 0x88(%RSP),%R11 |
(664) 0x474b05 MOV %RCX,(%R11,%R12,1) |
(664) 0x474b09 INC %RAX |
(664) 0x474b0c CMP (%R9),%RAX |
(664) 0x474b0f JGE 474b48 |
(664) 0x474b11 MOV (%R13,%RAX,8),%R12 |
(664) 0x474b16 MOV (%RDI,%R12,8),%RCX |
(664) 0x474b1a CMPQ $-0x3,(%R10,%RCX,8) |
(664) 0x474b1f JE 474aba |
(664) 0x474b21 CMPQ $0x1,0xe8(%RSP) |
(664) 0x474b2a JNE 474aa0 |
(664) 0x474b30 MOV 0xe0(%RSP),%R12 |
(664) 0x474b38 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(664) 0x474b3e JMP 474aba |
0x474b43 NOPL (%RAX,%RAX,1) |
(659) 0x474b48 MOV 0x78(%RSP),%R12 |
(659) 0x474b4d MOV 0x70(%RSP),%R11 |
(659) 0x474b52 MOV 0xb8(%RSP),%RDX |
(659) 0x474b5a MOV (%RDX),%R8 |
(659) 0x474b5d MOV 0xa0(%RSP),%R9 |
(659) 0x474b65 MOV 0xf0(%RSP),%RCX |
(659) 0x474b6d MOV (%R9),%RAX |
(659) 0x474b70 VMULSD (%RCX,%RAX,8),%XMM2,%XMM10 |
(659) 0x474b75 VCOMISD %XMM4,%XMM10 |
(659) 0x474b79 JE 474b84 |
(659) 0x474b7b VXORPD %XMM5,%XMM0,%XMM1 |
(659) 0x474b7f VDIVSD %XMM10,%XMM1,%XMM11 |
(659) 0x474b84 MOV 0xa8(%RSP),%RDI |
(659) 0x474b8c MOV 0xf8(%RSP),%RDX |
(659) 0x474b94 MOV (%RDI),%RCX |
(659) 0x474b97 CMP %RDX,%RCX |
(659) 0x474b9a JGE 474db6 |
(659) 0x474ba0 MOV %RDX,%R9 |
(659) 0x474ba3 MOV %RCX,0xb8(%RSP) |
(659) 0x474bab SUB %RCX,%R9 |
(659) 0x474bae LEA -0x1(%R9),%RAX |
(659) 0x474bb2 CMP $0x6,%RAX |
(659) 0x474bb6 JBE 4751e0 |
(659) 0x474bbc MOV 0xd0(%RSP),%RDI |
(659) 0x474bc4 MOV %R9,%RDX |
(659) 0x474bc7 VBROADCASTSD %XMM11,%ZMM12 |
(659) 0x474bcd SHR $0x3,%RDX |
(659) 0x474bd1 SAL $0x6,%RDX |
(659) 0x474bd5 LEA (%RDI,%RCX,8),%RAX |
(659) 0x474bd9 LEA (%RDX,%RAX,1),%RDI |
(659) 0x474bdd SUB $0x40,%RDX |
(659) 0x474be1 SHR $0x6,%RDX |
(659) 0x474be5 INC %RDX |
(659) 0x474be8 AND $0x7,%EDX |
(659) 0x474beb JE 474c95 |
(659) 0x474bf1 CMP $0x1,%RDX |
(659) 0x474bf5 JE 474c7f |
(659) 0x474bfb CMP $0x2,%RDX |
(659) 0x474bff JE 474c6e |
(659) 0x474c01 CMP $0x3,%RDX |
(659) 0x474c05 JE 474c5d |
(659) 0x474c07 CMP $0x4,%RDX |
(659) 0x474c0b JE 474c4c |
(659) 0x474c0d CMP $0x5,%RDX |
(659) 0x474c11 JE 474c3b |
(659) 0x474c13 CMP $0x6,%RDX |
(659) 0x474c17 JE 474c2a |
(659) 0x474c19 VMULPD (%RAX),%ZMM12,%ZMM13 |
(659) 0x474c1f ADD $0x40,%RAX |
(659) 0x474c23 VMOVUPD %ZMM13,-0x40(%RAX) |
(659) 0x474c2a VMULPD (%RAX),%ZMM12,%ZMM14 |
(659) 0x474c30 ADD $0x40,%RAX |
(659) 0x474c34 VMOVUPD %ZMM14,-0x40(%RAX) |
(659) 0x474c3b VMULPD (%RAX),%ZMM12,%ZMM15 |
(659) 0x474c41 ADD $0x40,%RAX |
(659) 0x474c45 VMOVUPD %ZMM15,-0x40(%RAX) |
(659) 0x474c4c VMULPD (%RAX),%ZMM12,%ZMM0 |
(659) 0x474c52 ADD $0x40,%RAX |
(659) 0x474c56 VMOVUPD %ZMM0,-0x40(%RAX) |
(659) 0x474c5d VMULPD (%RAX),%ZMM12,%ZMM3 |
(659) 0x474c63 ADD $0x40,%RAX |
(659) 0x474c67 VMOVUPD %ZMM3,-0x40(%RAX) |
(659) 0x474c6e VMULPD (%RAX),%ZMM12,%ZMM2 |
(659) 0x474c74 ADD $0x40,%RAX |
(659) 0x474c78 VMOVUPD %ZMM2,-0x40(%RAX) |
(659) 0x474c7f VMULPD (%RAX),%ZMM12,%ZMM6 |
(659) 0x474c85 ADD $0x40,%RAX |
(659) 0x474c89 VMOVUPD %ZMM6,-0x40(%RAX) |
(659) 0x474c90 CMP %RAX,%RDI |
(659) 0x474c93 JE 474d0f |
(661) 0x474c95 VMULPD (%RAX),%ZMM12,%ZMM7 |
(661) 0x474c9b ADD $0x200,%RAX |
(661) 0x474ca1 VMULPD -0x1c0(%RAX),%ZMM12,%ZMM8 |
(661) 0x474ca8 VMULPD -0x180(%RAX),%ZMM12,%ZMM9 |
(661) 0x474caf VMULPD -0x140(%RAX),%ZMM12,%ZMM10 |
(661) 0x474cb6 VMULPD -0x100(%RAX),%ZMM12,%ZMM1 |
(661) 0x474cbd VMULPD -0xc0(%RAX),%ZMM12,%ZMM13 |
(661) 0x474cc4 VMOVUPD %ZMM7,-0x200(%RAX) |
(661) 0x474ccb VMULPD -0x80(%RAX),%ZMM12,%ZMM14 |
(661) 0x474cd2 VMOVUPD %ZMM8,-0x1c0(%RAX) |
(661) 0x474cd9 VMULPD -0x40(%RAX),%ZMM12,%ZMM15 |
(661) 0x474ce0 VMOVUPD %ZMM9,-0x180(%RAX) |
(661) 0x474ce7 VMOVUPD %ZMM10,-0x140(%RAX) |
(661) 0x474cee VMOVUPD %ZMM1,-0x100(%RAX) |
(661) 0x474cf5 VMOVUPD %ZMM13,-0xc0(%RAX) |
(661) 0x474cfc VMOVUPD %ZMM14,-0x80(%RAX) |
(661) 0x474d03 VMOVUPD %ZMM15,-0x40(%RAX) |
(661) 0x474d0a CMP %RAX,%RDI |
(661) 0x474d0d JNE 474c95 |
(659) 0x474d0f MOV %R9,%RAX |
(659) 0x474d12 AND $-0x8,%RAX |
(659) 0x474d16 ADD %RAX,%RCX |
(659) 0x474d19 TEST $0x7,%R9B |
(659) 0x474d1d JE 474db6 |
(659) 0x474d23 SUB %RAX,%R9 |
(659) 0x474d26 LEA -0x1(%R9),%RDX |
(659) 0x474d2a CMP $0x2,%RDX |
(659) 0x474d2e JBE 474d64 |
(659) 0x474d30 MOV 0xb8(%RSP),%RDI |
(659) 0x474d38 MOV 0xd0(%RSP),%RDX |
(659) 0x474d40 VBROADCASTSD %XMM11,%YMM12 |
(659) 0x474d45 ADD %RAX,%RDI |
(659) 0x474d48 MOV %R9,%RAX |
(659) 0x474d4b LEA (%RDX,%RDI,8),%RDI |
(659) 0x474d4f AND $-0x4,%RAX |
(659) 0x474d53 VMULPD (%RDI),%YMM12,%YMM0 |
(659) 0x474d57 ADD %RAX,%RCX |
(659) 0x474d5a AND $0x3,%R9D |
(659) 0x474d5e VMOVUPD %YMM0,(%RDI) |
(659) 0x474d62 JE 474db6 |
(659) 0x474d64 MOV 0xd0(%RSP),%RDI |
(659) 0x474d6c LEA (,%RCX,8),%RAX |
(659) 0x474d74 LEA 0x1(%RCX),%RDX |
(659) 0x474d78 LEA (%RDI,%RAX,1),%R9 |
(659) 0x474d7c VMULSD (%R9),%XMM11,%XMM3 |
(659) 0x474d81 VMOVSD %XMM3,(%R9) |
(659) 0x474d86 MOV 0xf8(%RSP),%R9 |
(659) 0x474d8e CMP %RDX,%R9 |
(659) 0x474d91 JLE 474db6 |
(659) 0x474d93 LEA 0x8(%RDI,%RAX,1),%RDX |
(659) 0x474d98 ADD $0x2,%RCX |
(659) 0x474d9c VMULSD (%RDX),%XMM11,%XMM2 |
(659) 0x474da0 VMOVSD %XMM2,(%RDX) |
(659) 0x474da4 CMP %RCX,%R9 |
(659) 0x474da7 JLE 474db6 |
(659) 0x474da9 LEA 0x10(%RDI,%RAX,1),%RCX |
(659) 0x474dae VMULSD (%RCX),%XMM11,%XMM6 |
(659) 0x474db2 VMOVSD %XMM6,(%RCX) |
(659) 0x474db6 CMP %R8,%RSI |
(659) 0x474db9 JLE 474fbe |
(659) 0x474dbf MOV %RSI,%RCX |
(659) 0x474dc2 MOV %R8,%RDI |
(659) 0x474dc5 SUB %R8,%RCX |
(659) 0x474dc8 LEA -0x1(%RCX),%RAX |
(659) 0x474dcc CMP $0x6,%RAX |
(659) 0x474dd0 JBE 4751e7 |
(659) 0x474dd6 MOV 0xd8(%RSP),%RDX |
(659) 0x474dde VBROADCASTSD %XMM11,%ZMM7 |
(659) 0x474de4 LEA (%RDX,%R8,8),%RAX |
(659) 0x474de8 MOV %RCX,%RDX |
(659) 0x474deb SHR $0x3,%RDX |
(659) 0x474def SAL $0x6,%RDX |
(659) 0x474df3 LEA (%RDX,%RAX,1),%R9 |
(659) 0x474df7 SUB $0x40,%RDX |
(659) 0x474dfb SHR $0x6,%RDX |
(659) 0x474dff INC %RDX |
(659) 0x474e02 AND $0x7,%EDX |
(659) 0x474e05 JE 474eaf |
(659) 0x474e0b CMP $0x1,%RDX |
(659) 0x474e0f JE 474e99 |
(659) 0x474e15 CMP $0x2,%RDX |
(659) 0x474e19 JE 474e88 |
(659) 0x474e1b CMP $0x3,%RDX |
(659) 0x474e1f JE 474e77 |
(659) 0x474e21 CMP $0x4,%RDX |
(659) 0x474e25 JE 474e66 |
(659) 0x474e27 CMP $0x5,%RDX |
(659) 0x474e2b JE 474e55 |
(659) 0x474e2d CMP $0x6,%RDX |
(659) 0x474e31 JE 474e44 |
(659) 0x474e33 VMULPD (%RAX),%ZMM7,%ZMM8 |
(659) 0x474e39 ADD $0x40,%RAX |
(659) 0x474e3d VMOVUPD %ZMM8,-0x40(%RAX) |
(659) 0x474e44 VMULPD (%RAX),%ZMM7,%ZMM9 |
(659) 0x474e4a ADD $0x40,%RAX |
(659) 0x474e4e VMOVUPD %ZMM9,-0x40(%RAX) |
(659) 0x474e55 VMULPD (%RAX),%ZMM7,%ZMM10 |
(659) 0x474e5b ADD $0x40,%RAX |
(659) 0x474e5f VMOVUPD %ZMM10,-0x40(%RAX) |
(659) 0x474e66 VMULPD (%RAX),%ZMM7,%ZMM1 |
(659) 0x474e6c ADD $0x40,%RAX |
(659) 0x474e70 VMOVUPD %ZMM1,-0x40(%RAX) |
(659) 0x474e77 VMULPD (%RAX),%ZMM7,%ZMM13 |
(659) 0x474e7d ADD $0x40,%RAX |
(659) 0x474e81 VMOVUPD %ZMM13,-0x40(%RAX) |
(659) 0x474e88 VMULPD (%RAX),%ZMM7,%ZMM14 |
(659) 0x474e8e ADD $0x40,%RAX |
(659) 0x474e92 VMOVUPD %ZMM14,-0x40(%RAX) |
(659) 0x474e99 VMULPD (%RAX),%ZMM7,%ZMM15 |
(659) 0x474e9f ADD $0x40,%RAX |
(659) 0x474ea3 VMOVUPD %ZMM15,-0x40(%RAX) |
(659) 0x474eaa CMP %R9,%RAX |
(659) 0x474ead JE 474f29 |
(660) 0x474eaf VMULPD (%RAX),%ZMM7,%ZMM12 |
(660) 0x474eb5 ADD $0x200,%RAX |
(660) 0x474ebb VMULPD -0x1c0(%RAX),%ZMM7,%ZMM0 |
(660) 0x474ec2 VMULPD -0x180(%RAX),%ZMM7,%ZMM3 |
(660) 0x474ec9 VMULPD -0x140(%RAX),%ZMM7,%ZMM2 |
(660) 0x474ed0 VMULPD -0x100(%RAX),%ZMM7,%ZMM6 |
(660) 0x474ed7 VMULPD -0xc0(%RAX),%ZMM7,%ZMM8 |
(660) 0x474ede VMOVUPD %ZMM12,-0x200(%RAX) |
(660) 0x474ee5 VMULPD -0x80(%RAX),%ZMM7,%ZMM9 |
(660) 0x474eec VMOVUPD %ZMM0,-0x1c0(%RAX) |
(660) 0x474ef3 VMULPD -0x40(%RAX),%ZMM7,%ZMM10 |
(660) 0x474efa VMOVUPD %ZMM3,-0x180(%RAX) |
(660) 0x474f01 VMOVUPD %ZMM2,-0x140(%RAX) |
(660) 0x474f08 VMOVUPD %ZMM6,-0x100(%RAX) |
(660) 0x474f0f VMOVUPD %ZMM8,-0xc0(%RAX) |
(660) 0x474f16 VMOVUPD %ZMM9,-0x80(%RAX) |
(660) 0x474f1d VMOVUPD %ZMM10,-0x40(%RAX) |
(660) 0x474f24 CMP %R9,%RAX |
(660) 0x474f27 JNE 474eaf |
(659) 0x474f29 MOV %RCX,%R9 |
(659) 0x474f2c AND $-0x8,%R9 |
(659) 0x474f30 ADD %R9,%R8 |
(659) 0x474f33 TEST $0x7,%CL |
(659) 0x474f36 JE 474fbe |
(659) 0x474f3c SUB %R9,%RCX |
(659) 0x474f3f LEA -0x1(%RCX),%RAX |
(659) 0x474f43 CMP $0x2,%RAX |
(659) 0x474f47 JBE 474f74 |
(659) 0x474f49 ADD %RDI,%R9 |
(659) 0x474f4c MOV 0xd8(%RSP),%RDI |
(659) 0x474f54 VBROADCASTSD %XMM11,%YMM7 |
(659) 0x474f59 LEA (%RDI,%R9,8),%RDX |
(659) 0x474f5d MOV %RCX,%R9 |
(659) 0x474f60 VMULPD (%RDX),%YMM7,%YMM1 |
(659) 0x474f64 AND $-0x4,%R9 |
(659) 0x474f68 ADD %R9,%R8 |
(659) 0x474f6b AND $0x3,%ECX |
(659) 0x474f6e VMOVUPD %YMM1,(%RDX) |
(659) 0x474f72 JE 474fbe |
(659) 0x474f74 MOV 0xd8(%RSP),%RAX |
(659) 0x474f7c LEA (,%R8,8),%RCX |
(659) 0x474f84 LEA 0x1(%R8),%RDX |
(659) 0x474f88 LEA (%RAX,%RCX,1),%RDI |
(659) 0x474f8c VMULSD (%RDI),%XMM11,%XMM13 |
(659) 0x474f90 VMOVSD %XMM13,(%RDI) |
(659) 0x474f94 CMP %RDX,%RSI |
(659) 0x474f97 JLE 474fbe |
(659) 0x474f99 LEA 0x8(%RAX,%RCX,1),%R9 |
(659) 0x474f9e ADD $0x2,%R8 |
(659) 0x474fa2 VMULSD (%R9),%XMM11,%XMM14 |
(659) 0x474fa7 VMOVSD %XMM14,(%R9) |
(659) 0x474fac CMP %R8,%RSI |
(659) 0x474faf JLE 474fbe |
(659) 0x474fb1 LEA 0x10(%RAX,%RCX,1),%RSI |
(659) 0x474fb6 VMULSD (%RSI),%XMM11,%XMM15 |
(659) 0x474fba VMOVSD %XMM15,(%RSI) |
(659) 0x474fbe ADDQ $0x8,0xc8(%RSP) |
(659) 0x474fc7 MOV 0x30(%RSP),%RCX |
(659) 0x474fcc MOV 0xc8(%RSP),%R8 |
(659) 0x474fd4 CMP %RCX,%R8 |
(659) 0x474fd7 JNE 474660 |
0x474fdd VZEROUPPER |
0x474fe0 MOV %R12,%RDI |
0x474fe3 CALL 5b0950 <hypre_Free> |
0x474fe8 LEA -0x28(%RBP),%RSP |
0x474fec MOV %RBX,%RDI |
0x474fef POP %RBX |
0x474ff0 POP %R12 |
0x474ff2 POP %R13 |
0x474ff4 POP %R14 |
0x474ff6 POP %R15 |
0x474ff8 POP %RBP |
0x474ff9 JMP 5b0950 |
0x474ffe XCHG %AX,%AX |
(659) 0x475000 MOV %R10,0xb8(%RSP) |
(659) 0x475008 MOV %R8,0x78(%RSP) |
(659) 0x47500d MOV 0x10(%RSP),%R8 |
(659) 0x475012 MOV %R9,0x70(%RSP) |
(659) 0x475017 MOV 0xf8(%RSP),%R9 |
(659) 0x47501f NOP |
(666) 0x475020 MOV (%R11,%RAX,8),%RCX |
(666) 0x475024 CMPQ $-0x3,(%R8,%RCX,8) |
(666) 0x475029 JE 475039 |
(666) 0x47502b MOV 0xf0(%RSP),%R10 |
(666) 0x475033 VADDSD (%R10,%RAX,8),%XMM0,%XMM0 |
(666) 0x475039 CMP $-0x1,%RCX |
(666) 0x47503d JE 475088 |
(666) 0x47503f CMP (%R12,%RCX,8),%RDX |
(666) 0x475043 JNE 475088 |
(666) 0x475045 MOV 0xf0(%RSP),%R10 |
(666) 0x47504d LEA (,%R9,8),%RDI |
(666) 0x475055 VMOVSD (%R10,%RAX,8),%XMM3 |
(666) 0x47505b MOV 0xd0(%RSP),%R10 |
(666) 0x475063 VMOVSD %XMM3,(%R10,%R9,8) |
(666) 0x475069 MOV 0x98(%RSP),%R10 |
(666) 0x475071 VADDSD %XMM3,%XMM2,%XMM2 |
(666) 0x475075 INC %R9 |
(666) 0x475078 MOV (%R10,%RCX,8),%RCX |
(666) 0x47507c MOV 0x80(%RSP),%R10 |
(666) 0x475084 MOV %RCX,(%R10,%RDI,1) |
(666) 0x475088 INC %RAX |
(666) 0x47508b CMP (%RSI),%RAX |
(666) 0x47508e JL 475020 |
(659) 0x475090 MOV 0xb8(%RSP),%R10 |
(659) 0x475098 MOV 0x78(%RSP),%R8 |
(659) 0x47509d MOV %R9,0xf8(%RSP) |
(659) 0x4750a5 MOV 0x70(%RSP),%R9 |
(659) 0x4750aa JMP 4748fc |
0x4750af NOP |
(659) 0x4750b0 CMPQ $0x1,0xe8(%RSP) |
(659) 0x4750b9 JE 475160 |
(659) 0x4750bf MOV %R12,0x78(%RSP) |
(659) 0x4750c4 NOPL (%RAX) |
(663) 0x4750c8 MOV (%R13,%RAX,8),%RCX |
(663) 0x4750cd CMPQ $-0x3,(%R10,%RCX,8) |
(663) 0x4750d2 JE 4750fc |
(663) 0x4750d4 MOV 0xc0(%RSP),%RDI |
(663) 0x4750dc MOV 0xb0(%RSP),%R12 |
(663) 0x4750e4 MOV (%RDI,%R8,1),%RDI |
(663) 0x4750e8 CMP %RDI,(%R12,%RCX,8) |
(663) 0x4750ec JNE 4750fc |
(663) 0x4750ee MOV 0xe0(%RSP),%R12 |
(663) 0x4750f6 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(663) 0x4750fc CMP $-0x1,%RCX |
(663) 0x475100 JE 47514a |
(663) 0x475102 CMP (%RBX,%RCX,8),%RDX |
(663) 0x475106 JNE 47514a |
(663) 0x475108 MOV 0xe0(%RSP),%RDI |
(663) 0x475110 LEA (,%RSI,8),%R12 |
(663) 0x475118 VMOVSD (%RDI,%RAX,8),%XMM9 |
(663) 0x47511d MOV 0xd8(%RSP),%RDI |
(663) 0x475125 VMOVSD %XMM9,(%RDI,%RSI,8) |
(663) 0x47512a MOV 0x90(%RSP),%RDI |
(663) 0x475132 VADDSD %XMM9,%XMM2,%XMM2 |
(663) 0x475137 INC %RSI |
(663) 0x47513a MOV (%RDI,%RCX,8),%RCX |
(663) 0x47513e MOV 0x88(%RSP),%RDI |
(663) 0x475146 MOV %RCX,(%RDI,%R12,1) |
(663) 0x47514a INC %RAX |
(663) 0x47514d CMP %RAX,(%R9) |
(663) 0x475150 JG 4750c8 |
(659) 0x475156 MOV 0x78(%RSP),%R12 |
(659) 0x47515b JMP 474b52 |
(662) 0x475160 MOV (%R13,%RAX,8),%RCX |
(662) 0x475165 CMPQ $-0x3,(%R10,%RCX,8) |
(662) 0x47516a JE 47517a |
(662) 0x47516c MOV 0xe0(%RSP),%R8 |
(662) 0x475174 VADDSD (%R8,%RAX,8),%XMM0,%XMM0 |
(662) 0x47517a CMP $-0x1,%RCX |
(662) 0x47517e JE 4751c8 |
(662) 0x475180 CMP (%RBX,%RCX,8),%RDX |
(662) 0x475184 JNE 4751c8 |
(662) 0x475186 MOV 0xe0(%RSP),%RDI |
(662) 0x47518e LEA (,%RSI,8),%R8 |
(662) 0x475196 VMOVSD (%RDI,%RAX,8),%XMM8 |
(662) 0x47519b MOV 0xd8(%RSP),%RDI |
(662) 0x4751a3 VMOVSD %XMM8,(%RDI,%RSI,8) |
(662) 0x4751a8 MOV 0x90(%RSP),%RDI |
(662) 0x4751b0 VADDSD %XMM8,%XMM2,%XMM2 |
(662) 0x4751b5 INC %RSI |
(662) 0x4751b8 MOV (%RDI,%RCX,8),%RCX |
(662) 0x4751bc MOV 0x88(%RSP),%RDI |
(662) 0x4751c4 MOV %RCX,(%RDI,%R8,1) |
(662) 0x4751c8 INC %RAX |
(662) 0x4751cb CMP %RAX,(%R9) |
(662) 0x4751ce JG 475160 |
(659) 0x4751d0 JMP 474b52 |
0x4751d5 NOPL (%RAX) |
(659) 0x4751d8 MOV %RSI,%R8 |
(659) 0x4751db JMP 474b5d |
(659) 0x4751e0 XOR %EAX,%EAX |
(659) 0x4751e2 JMP 474d23 |
(659) 0x4751e7 XOR %R9D,%R9D |
(659) 0x4751ea JMP 474f3c |
0x4751ef MOV $0x8,%ESI |
0x4751f4 MOV %RBX,%RDI |
0x4751f7 MOV %R10,0x68(%RSP) |
0x4751fc MOV %R12,0x78(%RSP) |
0x475201 MOV %R11,0xa0(%RSP) |
0x475209 VMOVSD %XMM1,0xa8(%RSP) |
0x475212 MOV %RBX,0xb8(%RSP) |
0x47521a CALL 5b0890 <hypre_CAlloc> |
0x47521f MOV 0x78(%RSP),%RCX |
0x475224 MOV 0xb8(%RSP),%RDX |
0x47522c VMOVSD 0xa8(%RSP),%XMM1 |
0x475235 MOV 0xa0(%RSP),%R11 |
0x47523d MOV %RAX,%R12 |
0x475240 TEST %RCX,%RCX |
0x475243 MOV 0x68(%RSP),%R10 |
0x475248 JNE 4752fb |
0x47524e XOR %EBX,%EBX |
0x475250 TEST %RDX,%RDX |
0x475253 JLE 4745a2 |
0x475259 SAL $0x3,%RDX |
0x47525d MOV $0xff,%ESI |
0x475262 MOV %R12,%RDI |
0x475265 MOV %R10,0x78(%RSP) |
0x47526a MOV %RCX,0xa0(%RSP) |
0x475272 MOV %R11,0xa8(%RSP) |
0x47527a VMOVSD %XMM1,0xb8(%RSP) |
0x475283 CALL 4110a0 <memset@plt> |
0x475288 VMOVSD 0xb8(%RSP),%XMM1 |
0x475291 MOV 0xa8(%RSP),%R11 |
0x475299 MOV 0xa0(%RSP),%RCX |
0x4752a1 MOV 0x78(%RSP),%R10 |
0x4752a6 TEST %RCX,%RCX |
0x4752a9 JLE 4745a2 |
0x4752af LEA (,%RCX,8),%RDX |
0x4752b7 MOV $0xff,%ESI |
0x4752bc MOV %RBX,%RDI |
0x4752bf MOV %R10,0xa0(%RSP) |
0x4752c7 MOV %R11,0xa8(%RSP) |
0x4752cf VMOVSD %XMM1,0xb8(%RSP) |
0x4752d8 CALL 4110a0 <memset@plt> |
0x4752dd VMOVSD 0xb8(%RSP),%XMM1 |
0x4752e6 MOV 0xa8(%RSP),%R11 |
0x4752ee MOV 0xa0(%RSP),%R10 |
0x4752f6 JMP 4745a2 |
0x4752fb MOV %RCX,%RDI |
0x4752fe MOV $0x8,%ESI |
0x475303 MOV %R10,0x68(%RSP) |
0x475308 MOV %R11,0x78(%RSP) |
0x47530d MOV %RDX,0xa0(%RSP) |
0x475315 MOV %RCX,0xb8(%RSP) |
0x47531d VMOVSD %XMM1,0xa8(%RSP) |
0x475326 CALL 5b0890 <hypre_CAlloc> |
0x47532b MOV 0xa0(%RSP),%RDX |
0x475333 MOV 0xb8(%RSP),%RCX |
0x47533b VMOVSD 0xa8(%RSP),%XMM1 |
0x475344 MOV 0x78(%RSP),%R11 |
0x475349 MOV %RAX,%RBX |
0x47534c TEST %RDX,%RDX |
0x47534f MOV 0x68(%RSP),%R10 |
0x475354 JG 475259 |
0x47535a JMP 4752a6 |
0x47535f NOP |
0x475360 MOV %R12,%RDI |
0x475363 MOV $0x8,%ESI |
0x475368 MOV %R10,0x78(%RSP) |
0x47536d MOV %R11,0xa0(%RSP) |
0x475375 MOV %R12,0xb8(%RSP) |
0x47537d XOR %R12D,%R12D |
0x475380 VMOVSD %XMM1,0xa8(%RSP) |
0x475389 CALL 5b0890 <hypre_CAlloc> |
0x47538e MOV 0xb8(%RSP),%RCX |
0x475396 VMOVSD 0xa8(%RSP),%XMM1 |
0x47539f MOV 0xa0(%RSP),%R11 |
0x4753a7 MOV 0x78(%RSP),%R10 |
0x4753ac MOV %RAX,%RBX |
0x4753af JMP 4752a6 |
0x4753b4 NOPW %CS:(%RAX,%RAX,1) |
0x4753bf NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.20 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.80 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 205 |
nb uops | 218 |
loop length | 1086 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 36.33 cycles |
front end | 36.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.61-34.66 |
Stall cycles | 0.00 |
Front-end | 36.33 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 36.33 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4751ef <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdcf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 475360 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xf40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b39c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b39b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
DEC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 474fe0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x145800(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RCX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0950 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 4752fb <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xedb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4745a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4745a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4745a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xa0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 475259 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe39> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4752a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4752a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 205 |
nb uops | 218 |
loop length | 1086 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 36.33 cycles |
front end | 36.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.61-34.66 |
Stall cycles | 0.00 |
Front-end | 36.33 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 36.33 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4751ef <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdcf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 475360 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xf40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b39c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b39b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IDIV %RSI | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
DEC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 474fe0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x145800(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R9,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RCX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0950 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 4752fb <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xedb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4745a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 4745a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4745a2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x182> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xa0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x68(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 475259 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe39> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4752a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xa8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4752a6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.9– | 0.49 | 0.13 |
▼Loop 659 - par_multi_interp.c:1605-1660 - exec– | 0.09 | 0.02 |
○Loop 666 - par_multi_interp.c:1618-1628 - exec | 0.41 | 0.07 |
○Loop 663 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 664 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 660 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 661 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 667 - par_multi_interp.c:1618-1628 - exec | 0 | 0 |
○Loop 665 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 668 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 662 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |