Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/utilities/hypre_qsort.c: 31 - 187 |
-------------------------------------------------------------------------------- |
31: temp = v[i]; |
32: v[i] = v[j]; |
33: v[j] = temp; |
[...] |
175: if (left >= right) |
176: return; |
177: hypre_swap( v, left, (left+right)/2); |
178: last = left; |
179: for (i = left+1; i <= right; i++) |
180: if (v[i] < v[left]) |
181: { |
182: hypre_swap(v, ++last, i); |
183: } |
184: hypre_swap(v, left, last); |
185: hypre_qsort0(v, left, last-1); |
186: hypre_qsort0(v, last+1, right); |
187: } |
0x4d5e00 CMP %RDX,%RSI |
0x4d5e03 JGE 4d5f7c |
0x4d5e09 PUSH %RBP |
0x4d5e0a MOV %RSP,%RBP |
0x4d5e0d PUSH %R15 |
0x4d5e0f PUSH %R14 |
0x4d5e11 PUSH %R12 |
0x4d5e13 PUSH %RBX |
0x4d5e14 MOV %RDX,%RBX |
0x4d5e17 MOV %RDI,%R14 |
0x4d5e1a LEA 0x20(%RDI),%R15 |
0x4d5e1e MOV %RSI,%R12 |
0x4d5e21 JMP 4d5e5c |
0x4d5e23 NOPW %CS:(%RAX,%RAX,1) |
(4176) 0x4d5e30 MOV (%R14,%RSI,8),%RAX |
(4176) 0x4d5e34 MOV (%R14,%R12,8),%RCX |
(4176) 0x4d5e38 MOV %RCX,(%R14,%RSI,8) |
(4176) 0x4d5e3c MOV %RAX,(%R14,%R12,8) |
(4176) 0x4d5e40 LEA -0x1(%R12),%RDX |
(4176) 0x4d5e45 MOV %R14,%RDI |
(4176) 0x4d5e48 CALL 4d5e00 <hypre_qsort0> |
(4176) 0x4d5e4d INC %R12 |
(4176) 0x4d5e50 MOV %R12,%RSI |
(4176) 0x4d5e53 CMP %RBX,%R12 |
(4176) 0x4d5e56 JGE 4d5f74 |
(4176) 0x4d5e5c LEA (%RSI,%RBX,1),%RAX |
(4176) 0x4d5e60 MOV %RAX,%RCX |
(4176) 0x4d5e63 SHR $0x3f,%RCX |
(4176) 0x4d5e67 ADD %RAX,%RCX |
(4176) 0x4d5e6a MOV (%R14,%RSI,8),%RAX |
(4176) 0x4d5e6e AND $-0x2,%RCX |
(4176) 0x4d5e72 MOV (%R14,%RCX,4),%RDX |
(4176) 0x4d5e76 MOV %RDX,(%R14,%RSI,8) |
(4176) 0x4d5e7a MOV %RAX,(%R14,%RCX,4) |
(4176) 0x4d5e7e LEA 0x1(%RSI),%RAX |
(4176) 0x4d5e82 CMP %RAX,%RBX |
(4176) 0x4d5e85 CMOVG %RBX,%RAX |
(4176) 0x4d5e89 MOV %RAX,%RCX |
(4176) 0x4d5e8c SUB %RSI,%RCX |
(4176) 0x4d5e8f CMP $0x4,%RCX |
(4176) 0x4d5e93 JAE 4d5ee0 |
(4176) 0x4d5e95 MOV %RCX,%RDX |
(4176) 0x4d5e98 AND $-0x4,%RDX |
(4176) 0x4d5e9c CMP %RCX,%RDX |
(4176) 0x4d5e9f JAE 4d5e30 |
(4176) 0x4d5ea1 ADD %RSI,%RDX |
(4176) 0x4d5ea4 JMP 4d5ebc |
0x4d5ea6 NOPW %CS:(%RAX,%RAX,1) |
(4177) 0x4d5eb0 INC %RDX |
(4177) 0x4d5eb3 CMP %RDX,%RAX |
(4177) 0x4d5eb6 JE 4d5e30 |
(4177) 0x4d5ebc MOV 0x8(%R14,%RDX,8),%RCX |
(4177) 0x4d5ec1 CMP (%R14,%RSI,8),%RCX |
(4177) 0x4d5ec5 JGE 4d5eb0 |
(4177) 0x4d5ec7 MOV 0x8(%R14,%R12,8),%RDI |
(4177) 0x4d5ecc MOV %RCX,0x8(%R14,%R12,8) |
(4177) 0x4d5ed1 INC %R12 |
(4177) 0x4d5ed4 MOV %RDI,0x8(%R14,%RDX,8) |
(4177) 0x4d5ed9 JMP 4d5eb0 |
0x4d5edb NOPL (%RAX,%RAX,1) |
(4176) 0x4d5ee0 MOV %RCX,%RDX |
(4176) 0x4d5ee3 SHR $0x2,%RDX |
(4176) 0x4d5ee7 LEA (%R15,%RSI,8),%RDI |
(4176) 0x4d5eeb MOV %RSI,%R12 |
(4176) 0x4d5eee JMP 4d5ef9 |
(4178) 0x4d5ef0 ADD $0x20,%RDI |
(4178) 0x4d5ef4 DEC %RDX |
(4178) 0x4d5ef7 JE 4d5e95 |
(4178) 0x4d5ef9 MOV -0x18(%RDI),%R9 |
(4178) 0x4d5efd MOV (%R14,%RSI,8),%R8 |
(4178) 0x4d5f01 CMP %R8,%R9 |
(4178) 0x4d5f04 JGE 4d5f1b |
(4178) 0x4d5f06 MOV 0x8(%R14,%R12,8),%R8 |
(4178) 0x4d5f0b MOV %R9,0x8(%R14,%R12,8) |
(4178) 0x4d5f10 INC %R12 |
(4178) 0x4d5f13 MOV %R8,-0x18(%RDI) |
(4178) 0x4d5f17 MOV (%R14,%RSI,8),%R8 |
(4178) 0x4d5f1b MOV -0x10(%RDI),%R9 |
(4178) 0x4d5f1f CMP %R8,%R9 |
(4178) 0x4d5f22 JGE 4d5f39 |
(4178) 0x4d5f24 MOV 0x8(%R14,%R12,8),%R8 |
(4178) 0x4d5f29 MOV %R9,0x8(%R14,%R12,8) |
(4178) 0x4d5f2e INC %R12 |
(4178) 0x4d5f31 MOV %R8,-0x10(%RDI) |
(4178) 0x4d5f35 MOV (%R14,%RSI,8),%R8 |
(4178) 0x4d5f39 MOV -0x8(%RDI),%R9 |
(4178) 0x4d5f3d CMP %R8,%R9 |
(4178) 0x4d5f40 JGE 4d5f57 |
(4178) 0x4d5f42 MOV 0x8(%R14,%R12,8),%R8 |
(4178) 0x4d5f47 MOV %R9,0x8(%R14,%R12,8) |
(4178) 0x4d5f4c INC %R12 |
(4178) 0x4d5f4f MOV %R8,-0x8(%RDI) |
(4178) 0x4d5f53 MOV (%R14,%RSI,8),%R8 |
(4178) 0x4d5f57 MOV (%RDI),%R9 |
(4178) 0x4d5f5a CMP %R8,%R9 |
(4178) 0x4d5f5d JGE 4d5ef0 |
(4178) 0x4d5f5f MOV 0x8(%R14,%R12,8),%R8 |
(4178) 0x4d5f64 MOV %R9,0x8(%R14,%R12,8) |
(4178) 0x4d5f69 INC %R12 |
(4178) 0x4d5f6c MOV %R8,(%RDI) |
(4178) 0x4d5f6f JMP 4d5ef0 |
0x4d5f74 POP %RBX |
0x4d5f75 POP %R12 |
0x4d5f77 POP %R14 |
0x4d5f79 POP %R15 |
0x4d5f7b POP %RBP |
0x4d5f7c RET |
0x4d5f7d NOPL (%RAX) |
Path / |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 23 |
nb uops | 23 |
loop length | 75 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.83 cycles |
front end | 3.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 3.93-3.95 |
Stall cycles | 0.00 |
Front-end | 3.83 |
Dispatch | 2.50 |
Overall L1 | 3.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4d5f7c <hypre_qsort0+0x17c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4d5e5c <hypre_qsort0+0x5c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 23 |
nb uops | 23 |
loop length | 75 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.83 cycles |
front end | 3.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 3.93-3.95 |
Stall cycles | 0.00 |
Front-end | 3.83 |
Dispatch | 2.50 |
Overall L1 | 3.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4d5f7c <hypre_qsort0+0x17c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4d5e5c <hypre_qsort0+0x5c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_qsort0– | 0.01 | 0 |
▼Loop 4176 - hypre_qsort.c:31-186 - exec– | 0 | 0 |
○Loop 4178 - hypre_qsort.c:31-182 - exec | 0.01 | 0.05 |
○Loop 4177 - hypre_qsort.c:31-182 - exec | 0 | 0.01 |