Loop Id: 2454 | Module: exec | Source: par_csr_matop.c:897-915 [...] | Coverage: 0.01% |
---|
Loop Id: 2454 | Module: exec | Source: par_csr_matop.c:897-915 [...] | Coverage: 0.01% |
---|
0x53e550 MOV -0x60(%RBP),%R9 [6] |
0x53e554 MOV (%R9,%RAX,8),%RCX [1] |
0x53e558 LEA (%R12,%RCX,1),%RDX |
0x53e55c LEA (%R8,%RDX,8),%R9 |
0x53e560 MOV -0x68(%RBP),%RDX [6] |
0x53e564 MOV (%R9),%R15 [4] |
0x53e567 VMULSD (%RDX,%RAX,8),%XMM2,%XMM1 [3] |
0x53e56c CMP %R15,-0x40(%RBP) [6] |
0x53e570 JG 53e730 |
0x53e576 LEA (%R11,%R15,8),%RCX |
0x53e57a INC %RAX |
0x53e57d VADDSD (%RCX),%XMM1,%XMM4 [2] |
0x53e581 VMOVSD %XMM4,(%RCX) [2] |
0x53e585 CMP %R10,%RAX |
0x53e588 JL 53e550 |
0x53e730 MOV %RSI,(%R9) [4] |
0x53e733 MOV -0x80(%RBP),%R10 [6] |
0x53e737 INC %RAX |
0x53e73a MOV -0xa8(%RBP),%R9 [6] |
0x53e741 VMOVSD %XMM1,(%R11,%RSI,8) [5] |
0x53e747 MOV %RCX,(%R10,%RSI,8) [7] |
0x53e74b INC %RSI |
0x53e74e MOV (%R9),%R10 [8] |
0x53e751 CMP %R10,%RAX |
0x53e754 JL 53e550 |
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 897 - 915 |
-------------------------------------------------------------------------------- |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.89 |
CQA speedup if FP arith vectorized | 2.13 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:897-899,par_csr_matop.c:907-915 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.83 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 1.33 |
CQA cycles if fully vectorized | 0.35 |
Front-end cycles | 2.83 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.75 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 1.00 |
P4 cycles | 0.65 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.60 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.31 |
Stall cycles (UFS) | 0.26 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 8.00 |
Nb stores | 2.00 |
Nb stack references | 4.00 |
FLOP/cycle | 0.53 |
Nb FLOP add-sub | 0.50 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.96 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 16.00 |
Stride 0 | 1.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 1.50 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.67 |
CQA speedup if FP arith vectorized | 2.14 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:897-899,par_csr_matop.c:907-915 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.50 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 1.17 |
CQA cycles if fully vectorized | 0.31 |
Front-end cycles | 2.50 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 1.00 |
P1 cycles | 2.33 |
P2 cycles | 2.33 |
P3 cycles | 0.50 |
P4 cycles | 0.70 |
P5 cycles | 1.00 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 0.80 |
P10 cycles | 2.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.09 |
Stall cycles (UFS) | 0.38 |
Nb insns | 15.00 |
Nb uops | 14.00 |
Nb loads | 7.00 |
Nb stores | 1.00 |
Nb stack references | 3.00 |
FLOP/cycle | 0.80 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 8.00 |
Stride 0 | 1.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 2.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.11 |
CQA speedup if FP arith vectorized | 2.11 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:897-899,par_csr_matop.c:907-915 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.17 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 1.50 |
CQA cycles if fully vectorized | 0.40 |
Front-end cycles | 3.17 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.50 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 1.50 |
P4 cycles | 0.60 |
P5 cycles | 1.00 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 0.40 |
P10 cycles | 3.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.52 |
Stall cycles (UFS) | 0.14 |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 9.00 |
Nb stores | 3.00 |
Nb stack references | 5.00 |
FLOP/cycle | 0.32 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 30.32 |
Bytes prefetched | 0.00 |
Bytes loaded | 72.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 1.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:897-915 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 69 |
used x86 registers | 10.50 |
used mmx registers | 0 |
used xmm registers | 2.50 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 4 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 2.83 cycles |
front end | 2.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.75 | 2.67 | 2.67 | 1.00 | 0.65 | 1.00 | 1.00 | 1.00 | 1.00 | 0.60 | 2.67 |
cycles | 1.50 | 0.75 | 2.67 | 2.67 | 1.00 | 0.65 | 1.00 | 1.00 | 1.00 | 1.00 | 0.60 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.30 |
Stall cycles | 0.26 |
LM full (events) | 0.78 |
Front-end | 2.83 |
Dispatch | 2.67 |
Data deps. | 1.00 |
Overall L1 | 2.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:897-915 |
Module | exec |
nb instructions | 15 |
nb uops | 14 |
loop length | 58 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 3 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 2.50 cycles |
front end | 2.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.00 | 2.33 | 2.33 | 0.50 | 0.70 | 1.00 | 0.50 | 0.50 | 0.50 | 0.80 | 2.33 |
cycles | 1.50 | 1.00 | 2.33 | 2.33 | 0.50 | 0.70 | 1.00 | 0.50 | 0.50 | 0.50 | 0.80 | 2.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.09 |
Stall cycles | 0.38 |
LM full (events) | 1.08 |
Front-end | 2.50 |
Dispatch | 2.33 |
Data deps. | 1.00 |
Overall L1 | 2.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9,%RAX,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%RCX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R8,%RDX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x68(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%RDX,%RAX,8),%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
CMP %R15,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 53e730 <hypre_ParMatmul._omp_fn.3+0x5c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R11,%R15,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VADDSD (%RCX),%XMM1,%XMM4 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM4,(%RCX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 53e550 <hypre_ParMatmul._omp_fn.3+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:897-915 |
Module | exec |
nb instructions | 19 |
nb uops | 18 |
loop length | 80 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 5 |
micro-operation queue | 3.17 cycles |
front end | 3.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.50 | 3.00 | 3.00 | 1.50 | 0.60 | 1.00 | 1.50 | 1.50 | 1.50 | 0.40 | 3.00 |
cycles | 1.50 | 0.50 | 3.00 | 3.00 | 1.50 | 0.60 | 1.00 | 1.50 | 1.50 | 1.50 | 0.40 | 3.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.52 |
Stall cycles | 0.14 |
LM full (events) | 0.48 |
Front-end | 3.17 |
Dispatch | 3.00 |
Data deps. | 1.00 |
Overall L1 | 3.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9,%RAX,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%RCX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R8,%RDX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x68(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%RDX,%RAX,8),%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
CMP %R15,-0x40(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JG 53e730 <hypre_ParMatmul._omp_fn.3+0x5c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,(%R9) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x80(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0xa8(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM1,(%R11,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R9),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 53e550 <hypre_ParMatmul._omp_fn.3+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |