Loop Id: 3392 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.04% |
---|
Loop Id: 3392 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.04% |
---|
0x4b0450 MOV %RCX,-0x30(%RBP) |
0x4b0454 MOV %RAX,%R14 |
0x4b0457 MOV -0x48(%RBP),%RCX |
0x4b045b CMP %RCX,%R12 |
0x4b045e JGE 4b07ad |
0x4b0464 MOV %R12,%RDX |
0x4b0467 CMPQ $0,-0xb8(%RBP) |
0x4b046f JE 4b0489 |
0x4b0471 MOV %R14,(%RDI,%RDX,8) |
0x4b0475 MOVQ $0,(%R15,%R14,8) |
0x4b047d MOV -0x50(%RBP),%RAX |
0x4b0481 MOV %RDX,(%RAX,%R14,8) |
0x4b0485 LEA 0x1(%R14),%RAX |
0x4b0489 CMPQ $0,-0xb0(%RBP) |
0x4b0491 JE 4b0620 |
0x4b0497 MOV -0x58(%RBP),%RCX |
0x4b049b MOV (%RCX,%RDX,8),%RSI |
0x4b049f LEA 0x1(%RDX),%R12 |
0x4b04a3 CMP 0x8(%RCX,%RDX,8),%RSI |
0x4b04a8 JGE 4b0624 |
0x4b04ae MOV %R12,-0x38(%RBP) |
0x4b04b2 MOV -0x30(%RBP),%RCX |
0x4b04b6 MOV %RDX,-0x40(%RBP) |
0x4b04ba JMP 4b04d9 |
(3396) 0x4b04c0 MOV %R12,%RSI |
(3396) 0x4b04c3 INC %RSI |
(3396) 0x4b04c6 MOV -0x58(%RBP),%RDX |
(3396) 0x4b04ca MOV -0x40(%RBP),%R12 |
(3396) 0x4b04ce CMP 0x8(%RDX,%R12,8),%RSI |
(3396) 0x4b04d3 JGE 4b0630 |
(3396) 0x4b04d9 MOV -0xc0(%RBP),%RDX |
(3396) 0x4b04e0 MOV (%RDX,%RSI,8),%R8 |
(3396) 0x4b04e4 MOV -0xc8(%RBP),%RDX |
(3396) 0x4b04eb MOV %RSI,%R12 |
(3396) 0x4b04ee VMOVSD (%RDX,%RSI,8),%XMM0 |
(3396) 0x4b04f3 MOV -0x78(%RBP),%RDX |
(3396) 0x4b04f7 MOV (%RDX,%R8,8),%R9 |
(3396) 0x4b04fb MOV 0x8(%RDX,%R8,8),%R10 |
(3396) 0x4b0500 CMP %R10,%R9 |
(3396) 0x4b0503 JL 4b0545 |
(3396) 0x4b0505 JMP 4b057e |
(3398) 0x4b0510 MOV %RCX,(%RDI,%RSI,8) |
(3398) 0x4b0514 MOV -0xa0(%RBP),%RDX |
(3398) 0x4b051b VMULSD (%RDX,%R9,8),%XMM0,%XMM1 |
(3398) 0x4b0521 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3398) 0x4b0526 MOV -0x90(%RBP),%RDX |
(3398) 0x4b052d MOV %R11,(%RDX,%RCX,8) |
(3398) 0x4b0531 INC %RCX |
(3398) 0x4b0534 MOV -0x78(%RBP),%RDX |
(3398) 0x4b0538 MOV 0x8(%RDX,%R8,8),%R10 |
(3398) 0x4b053d INC %R9 |
(3398) 0x4b0540 CMP %R10,%R9 |
(3398) 0x4b0543 JGE 4b057e |
(3398) 0x4b0545 MOV -0x100(%RBP),%RDX |
(3398) 0x4b054c MOV (%RDX,%R9,8),%R11 |
(3398) 0x4b0550 LEA (%R11,%R13,1),%RSI |
(3398) 0x4b0554 MOV (%RDI,%RSI,8),%RDX |
(3398) 0x4b0558 CMP -0x30(%RBP),%RDX |
(3398) 0x4b055c JL 4b0510 |
(3398) 0x4b055e MOV -0xa0(%RBP),%RSI |
(3398) 0x4b0565 VMOVSD (%RSI,%R9,8),%XMM1 |
(3398) 0x4b056b VFMADD213SD (%RBX,%RDX,8),%XMM0,%XMM1 |
(3398) 0x4b0571 VMOVSD %XMM1,(%RBX,%RDX,8) |
(3398) 0x4b0576 INC %R9 |
(3398) 0x4b0579 CMP %R10,%R9 |
(3398) 0x4b057c JL 4b0545 |
(3396) 0x4b057e MOV -0x70(%RBP),%RDX |
(3396) 0x4b0582 MOV (%RDX,%R8,8),%R9 |
(3396) 0x4b0586 MOV 0x8(%RDX,%R8,8),%R10 |
(3396) 0x4b058b CMP %R10,%R9 |
(3396) 0x4b058e JL 4b05d7 |
(3396) 0x4b0590 JMP 4b04c0 |
(3397) 0x4b05a0 MOV %RAX,(%RDI,%R11,8) |
(3397) 0x4b05a4 MOV -0x98(%RBP),%RDX |
(3397) 0x4b05ab VMULSD (%RDX,%R9,8),%XMM0,%XMM1 |
(3397) 0x4b05b1 VMOVSD %XMM1,(%R15,%RAX,8) |
(3397) 0x4b05b7 MOV -0x50(%RBP),%RDX |
(3397) 0x4b05bb MOV %R11,(%RDX,%RAX,8) |
(3397) 0x4b05bf INC %RAX |
(3397) 0x4b05c2 MOV -0x70(%RBP),%RDX |
(3397) 0x4b05c6 MOV 0x8(%RDX,%R8,8),%R10 |
(3397) 0x4b05cb INC %R9 |
(3397) 0x4b05ce CMP %R10,%R9 |
(3397) 0x4b05d1 JGE 4b04c0 |
(3397) 0x4b05d7 MOV -0xf8(%RBP),%RDX |
(3397) 0x4b05de MOV (%RDX,%R9,8),%R11 |
(3397) 0x4b05e2 MOV (%RDI,%R11,8),%RDX |
(3397) 0x4b05e6 CMP %R14,%RDX |
(3397) 0x4b05e9 JL 4b05a0 |
(3397) 0x4b05eb MOV -0x98(%RBP),%RSI |
(3397) 0x4b05f2 VMOVSD (%RSI,%R9,8),%XMM1 |
(3397) 0x4b05f8 VFMADD213SD (%R15,%RDX,8),%XMM0,%XMM1 |
(3397) 0x4b05fe VMOVSD %XMM1,(%R15,%RDX,8) |
(3397) 0x4b0604 INC %R9 |
(3397) 0x4b0607 CMP %R10,%R9 |
(3397) 0x4b060a JL 4b05d7 |
(3396) 0x4b060c JMP 4b04c0 |
0x4b0620 LEA 0x1(%RDX),%R12 |
0x4b0624 MOV -0x30(%RBP),%RCX |
0x4b0628 JMP 4b0637 |
0x4b0630 MOV %R12,%RDX |
0x4b0633 MOV -0x38(%RBP),%R12 |
0x4b0637 MOV -0x60(%RBP),%RSI |
0x4b063b MOV (%RSI,%RDX,8),%RDX |
0x4b063f CMP (%RSI,%R12,8),%RDX |
0x4b0643 JGE 4b0450 |
0x4b0649 MOV %R12,-0x38(%RBP) |
0x4b064d JMP 4b0665 |
(3393) 0x4b0650 INC %RDX |
(3393) 0x4b0653 MOV -0x60(%RBP),%RSI |
(3393) 0x4b0657 MOV -0x38(%RBP),%R12 |
(3393) 0x4b065b CMP (%RSI,%R12,8),%RDX |
(3393) 0x4b065f JGE 4b0450 |
(3393) 0x4b0665 MOV -0xe0(%RBP),%RSI |
(3393) 0x4b066c MOV (%RSI,%RDX,8),%RSI |
(3393) 0x4b0670 MOV -0xd8(%RBP),%R8 |
(3393) 0x4b0677 VMOVSD (%R8,%RDX,8),%XMM0 |
(3393) 0x4b067d MOV -0x80(%RBP),%R9 |
(3393) 0x4b0681 MOV (%R9,%RSI,8),%R8 |
(3393) 0x4b0685 MOV 0x8(%R9,%RSI,8),%R9 |
(3393) 0x4b068a CMP %R9,%R8 |
(3393) 0x4b068d JL 4b06d3 |
(3393) 0x4b068f JMP 4b0708 |
(3395) 0x4b06a0 MOV %RAX,(%RDI,%R10,8) |
(3395) 0x4b06a4 MOV -0xa8(%RBP),%R9 |
(3395) 0x4b06ab VMULSD (%R9,%R8,8),%XMM0,%XMM1 |
(3395) 0x4b06b1 VMOVSD %XMM1,(%R15,%RAX,8) |
(3395) 0x4b06b7 MOV -0x50(%RBP),%R9 |
(3395) 0x4b06bb MOV %R10,(%R9,%RAX,8) |
(3395) 0x4b06bf INC %RAX |
(3395) 0x4b06c2 MOV -0x80(%RBP),%R9 |
(3395) 0x4b06c6 MOV 0x8(%R9,%RSI,8),%R9 |
(3395) 0x4b06cb INC %R8 |
(3395) 0x4b06ce CMP %R9,%R8 |
(3395) 0x4b06d1 JGE 4b0708 |
(3395) 0x4b06d3 MOV -0x108(%RBP),%R10 |
(3395) 0x4b06da MOV (%R10,%R8,8),%R10 |
(3395) 0x4b06de MOV (%RDI,%R10,8),%R11 |
(3395) 0x4b06e2 CMP %R14,%R11 |
(3395) 0x4b06e5 JL 4b06a0 |
(3395) 0x4b06e7 MOV -0xa8(%RBP),%R10 |
(3395) 0x4b06ee VMOVSD (%R10,%R8,8),%XMM1 |
(3395) 0x4b06f4 VFMADD213SD (%R15,%R11,8),%XMM0,%XMM1 |
(3395) 0x4b06fa VMOVSD %XMM1,(%R15,%R11,8) |
(3395) 0x4b0700 INC %R8 |
(3395) 0x4b0703 CMP %R9,%R8 |
(3395) 0x4b0706 JL 4b06d3 |
(3393) 0x4b0708 CMPQ $0,-0xd0(%RBP) |
(3393) 0x4b0710 JE 4b0650 |
(3393) 0x4b0716 MOV -0x68(%RBP),%R9 |
(3393) 0x4b071a MOV (%R9,%RSI,8),%R8 |
(3393) 0x4b071e MOV 0x8(%R9,%RSI,8),%R9 |
(3393) 0x4b0723 JMP 4b074f |
(3394) 0x4b0730 MOV -0x88(%RBP),%R10 |
(3394) 0x4b0737 VMOVSD (%R10,%R8,8),%XMM1 |
(3394) 0x4b073d VFMADD213SD (%RBX,%R11,8),%XMM0,%XMM1 |
(3394) 0x4b0743 VMOVSD %XMM1,(%RBX,%R11,8) |
(3394) 0x4b0749 MOV %R12,%R13 |
(3394) 0x4b074c INC %R8 |
(3394) 0x4b074f CMP %R9,%R8 |
(3394) 0x4b0752 JGE 4b0650 |
(3394) 0x4b0758 MOV -0xe8(%RBP),%R10 |
(3394) 0x4b075f MOV (%R10,%R8,8),%R10 |
(3394) 0x4b0763 MOV -0xf0(%RBP),%R11 |
(3394) 0x4b076a MOV (%R11,%R10,8),%R10 |
(3394) 0x4b076e MOV %R13,%R12 |
(3394) 0x4b0771 ADD %R10,%R13 |
(3394) 0x4b0774 MOV (%RDI,%R13,8),%R11 |
(3394) 0x4b0778 CMP -0x30(%RBP),%R11 |
(3394) 0x4b077c JGE 4b0730 |
(3394) 0x4b077e MOV %RCX,(%RDI,%R13,8) |
(3394) 0x4b0782 MOV -0x88(%RBP),%R9 |
(3394) 0x4b0789 VMULSD (%R9,%R8,8),%XMM0,%XMM1 |
(3394) 0x4b078f VMOVSD %XMM1,(%RBX,%RCX,8) |
(3394) 0x4b0794 MOV -0x90(%RBP),%R9 |
(3394) 0x4b079b MOV %R10,(%R9,%RCX,8) |
(3394) 0x4b079f INC %RCX |
(3394) 0x4b07a2 MOV -0x68(%RBP),%R9 |
(3394) 0x4b07a6 MOV 0x8(%R9,%RSI,8),%R9 |
(3394) 0x4b07ab JMP 4b0749 |
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
875: { |
876: B_marker[i1] = jj_count_diag; |
877: C_diag_data[jj_count_diag] = zero; |
878: C_diag_j[jj_count_diag] = i1; |
879: jj_count_diag++; |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.44 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.17 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 6.17 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.80 |
P1 cycles | 4.33 |
P2 cycles | 4.33 |
P3 cycles | 3.50 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 3.50 |
P7 cycles | 3.50 |
P8 cycles | 3.50 |
P9 cycles | 1.60 |
P10 cycles | 4.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.32 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | 13.00 |
Nb stores | 7.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.95 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.93 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.44 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.17 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 6.17 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.80 |
P1 cycles | 4.33 |
P2 cycles | 4.33 |
P3 cycles | 3.50 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 3.50 |
P7 cycles | 3.50 |
P8 cycles | 3.50 |
P9 cycles | 1.60 |
P10 cycles | 4.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.32 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | 13.00 |
Nb stores | 7.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.95 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.93 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 35 |
nb uops | 35 |
loop length | 149 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.80 | 4.33 | 4.33 | 3.50 | 1.60 | 2.50 | 3.50 | 3.50 | 3.50 | 1.60 | 4.33 |
cycles | 2.50 | 1.80 | 4.33 | 4.33 | 3.50 | 1.60 | 2.50 | 3.50 | 3.50 | 3.50 | 1.60 | 4.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.32 |
Stall cycles | 0.00 |
Front-end | 6.17 |
Dispatch | 4.33 |
Overall L1 | 6.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4b07ad <hypre_ParMatmul.extracted.12+0x57d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,-0xb8(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0489 <hypre_ParMatmul.extracted.12+0x259> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R15,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RAX,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R14),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0xb0(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0620 <hypre_ParMatmul.extracted.12+0x3f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RCX,%RDX,8),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b0624 <hypre_ParMatmul.extracted.12+0x3f4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b04d9 <hypre_ParMatmul.extracted.12+0x2a9> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDX),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4b0637 <hypre_ParMatmul.extracted.12+0x407> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x38(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RSI,%R12,8),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b0450 <hypre_ParMatmul.extracted.12+0x220> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b0665 <hypre_ParMatmul.extracted.12+0x435> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 35 |
nb uops | 35 |
loop length | 149 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.80 | 4.33 | 4.33 | 3.50 | 1.60 | 2.50 | 3.50 | 3.50 | 3.50 | 1.60 | 4.33 |
cycles | 2.50 | 1.80 | 4.33 | 4.33 | 3.50 | 1.60 | 2.50 | 3.50 | 3.50 | 3.50 | 1.60 | 4.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.32 |
Stall cycles | 0.00 |
Front-end | 6.17 |
Dispatch | 4.33 |
Overall L1 | 6.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4b07ad <hypre_ParMatmul.extracted.12+0x57d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,-0xb8(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0489 <hypre_ParMatmul.extracted.12+0x259> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R15,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RAX,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R14),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0xb0(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0620 <hypre_ParMatmul.extracted.12+0x3f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RCX,%RDX,8),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b0624 <hypre_ParMatmul.extracted.12+0x3f4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b04d9 <hypre_ParMatmul.extracted.12+0x2a9> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDX),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4b0637 <hypre_ParMatmul.extracted.12+0x407> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x38(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RSI,%R12,8),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b0450 <hypre_ParMatmul.extracted.12+0x220> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b0665 <hypre_ParMatmul.extracted.12+0x435> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |