Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.44% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.44% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1584: tmp_marker = NULL; |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
1600: { thread_stop = pass_pointer[1] + pass_length; } |
1601: else |
1602: { thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); } |
1603: |
1604: /* determine P for points of pass 1, i.e. neighbors of coarse points */ |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x46efc0 PUSH %RBP |
0x46efc1 MOV %RSP,%RBP |
0x46efc4 PUSH %R15 |
0x46efc6 PUSH %R14 |
0x46efc8 PUSH %R13 |
0x46efca PUSH %R12 |
0x46efcc PUSH %RBX |
0x46efcd AND $-0x20,%RSP |
0x46efd1 SUB $0x100,%RSP |
0x46efd8 MOV 0xf8(%RDI),%RAX |
0x46efdf MOV 0xe0(%RDI),%RCX |
0x46efe6 MOV 0xd8(%RDI),%RSI |
0x46efed MOV 0xd0(%RDI),%R8 |
0x46eff4 MOV 0xc8(%RDI),%R9 |
0x46effb MOV 0xc0(%RDI),%R10 |
0x46f002 MOV %RAX,0xe0(%RSP) |
0x46f00a MOV 0xb8(%RDI),%R11 |
0x46f011 MOV 0xb0(%RDI),%R12 |
0x46f018 MOV %RCX,0x8(%RSP) |
0x46f01d MOV 0xa8(%RDI),%R13 |
0x46f024 MOV 0x90(%RDI),%RAX |
0x46f02b MOV %RSI,0xa0(%RSP) |
0x46f033 MOV 0xf0(%RDI),%RDX |
0x46f03a MOV %R8,0x38(%RSP) |
0x46f03f MOV %R9,0x30(%RSP) |
0x46f044 MOV 0xe8(%RDI),%RBX |
0x46f04b MOV %R10,0x70(%RSP) |
0x46f050 MOV 0xa0(%RDI),%R14 |
0x46f057 MOV %R11,0x68(%RSP) |
0x46f05c MOV 0x98(%RDI),%R15 |
0x46f063 MOV %R12,0xd8(%RSP) |
0x46f06b MOV %R13,0x80(%RSP) |
0x46f073 MOV %RAX,0xc8(%RSP) |
0x46f07b MOV %RDX,0xa8(%RSP) |
0x46f083 MOV 0x88(%RDI),%RDX |
0x46f08a MOV 0x80(%RDI),%RCX |
0x46f091 MOV 0x78(%RDI),%RSI |
0x46f095 MOV 0x68(%RDI),%R8 |
0x46f099 MOV 0x60(%RDI),%R9 |
0x46f09d MOV %RDX,0x28(%RSP) |
0x46f0a2 MOV 0x40(%RDI),%RAX |
0x46f0a6 MOV 0x38(%RDI),%RDX |
0x46f0aa MOV %RSI,0x60(%RSP) |
0x46f0af MOV 0x70(%RDI),%R10 |
0x46f0b3 MOV 0x28(%RDI),%RSI |
0x46f0b7 MOV %R9,0x58(%RSP) |
0x46f0bc MOV %RCX,0x98(%RSP) |
0x46f0c4 MOV 0x18(%RDI),%R9 |
0x46f0c8 MOV 0x30(%RDI),%RCX |
0x46f0cc MOV %R8,0x90(%RSP) |
0x46f0d4 MOV 0x58(%RDI),%R11 |
0x46f0d8 MOV 0x20(%RDI),%R8 |
0x46f0dc MOV %RAX,0x50(%RSP) |
0x46f0e1 MOV 0x50(%RDI),%R12 |
0x46f0e5 MOV 0x10(%RDI),%RAX |
0x46f0e9 MOV %RCX,0x20(%RSP) |
0x46f0ee MOV %RDX,0xe8(%RSP) |
0x46f0f6 MOV 0x48(%RDI),%R13 |
0x46f0fa MOV 0x8(%RDI),%RDX |
0x46f0fe MOV (%RDI),%RDI |
0x46f101 MOV %RSI,0x48(%RSP) |
0x46f106 MOV %R8,0xf8(%RSP) |
0x46f10e MOV %R9,0x18(%RSP) |
0x46f113 MOV %RAX,0xd0(%RSP) |
0x46f11b MOV %RDX,0xf0(%RSP) |
0x46f123 MOV %RDI,0x10(%RSP) |
0x46f128 TEST %RBX,%RBX |
0x46f12b JNE 46fd0e |
0x46f131 TEST %R12,%R12 |
0x46f134 JNE 46fe90 |
0x46f13a XOR %EBX,%EBX |
0x46f13c XOR %R12D,%R12D |
0x46f13f MOV %R11,0x88(%RSP) |
0x46f147 MOV %R10,0xb0(%RSP) |
0x46f14f VMOVSD %XMM1,0xb8(%RSP) |
0x46f158 CALL 592810 <hypre_GetThreadNum> |
0x46f15d MOV %RAX,0xc0(%RSP) |
0x46f165 CALL 592800 <hypre_NumActiveThreads> |
0x46f16a MOV 0xc0(%RSP),%R10 |
0x46f172 MOV 0xd8(%RSP),%R8 |
0x46f17a MOV %RAX,%R9 |
0x46f17d MOV 0xe0(%RSP),%RAX |
0x46f185 MOV 0xe0(%RSP),%RSI |
0x46f18d VMOVSD 0xb8(%RSP),%XMM11 |
0x46f196 MOV %R10,%R11 |
0x46f199 MOV 0x8(%R8),%RCX |
0x46f19d CQTO |
0x46f19f IDIV %R9 |
0x46f1a2 ADD %RCX,%RSI |
0x46f1a5 DEC %R9 |
0x46f1a8 MOV %RSI,%R8 |
0x46f1ab IMUL %RAX,%R11 |
0x46f1af ADD %R11,%RAX |
0x46f1b2 LEA (%RCX,%R11,1),%RDI |
0x46f1b6 MOV 0x88(%RSP),%R11 |
0x46f1be ADD %RCX,%RAX |
0x46f1c1 CMP %R9,%R10 |
0x46f1c4 MOV 0xb0(%RSP),%R10 |
0x46f1cc CMOVNE %RAX,%R8 |
0x46f1d0 CMP %RDI,%R8 |
0x46f1d3 JLE 46fabe |
0x46f1d9 MOV 0x80(%RSP),%R9 |
0x46f1e1 VMOVQ 0x129b57(%RIP),%XMM5 |
0x46f1e9 VXORPD %XMM4,%XMM4,%XMM4 |
0x46f1ed LEA (%R9,%RDI,8),%RCX |
0x46f1f1 LEA (%R9,%R8,8),%RAX |
0x46f1f5 MOV %RCX,0xd8(%RSP) |
0x46f1fd MOV %RAX,0x40(%RSP) |
0x46f202 NOPW (%RAX,%RAX,1) |
(658) 0x46f208 MOV 0xd8(%RSP),%RDX |
(658) 0x46f210 MOV 0x58(%RSP),%RCX |
(658) 0x46f215 MOV 0x68(%RSP),%RDI |
(658) 0x46f21a MOV (%RDX),%RDX |
(658) 0x46f21d LEA (,%RDX,8),%R8 |
(658) 0x46f225 MOV (%RDI,%RDX,8),%R9 |
(658) 0x46f229 LEA (%RCX,%R8,1),%RAX |
(658) 0x46f22d LEA 0x8(%R8),%RSI |
(658) 0x46f231 MOV (%RAX),%RDI |
(658) 0x46f234 MOV %RAX,0xc0(%RSP) |
(658) 0x46f23c MOV 0x8(%RCX,%R8,1),%RAX |
(658) 0x46f241 MOV %RSI,0xe0(%RSP) |
(658) 0x46f249 ADD %R9,%RAX |
(658) 0x46f24c SUB %RDI,%RAX |
(658) 0x46f24f CMP %RAX,%R9 |
(658) 0x46f252 JGE 46f399 |
(658) 0x46f258 MOV 0x30(%RSP),%RDI |
(658) 0x46f25d MOV 0x8(%RDI),%RSI |
(658) 0x46f261 LEA (%RSI,%RAX,8),%RDI |
(658) 0x46f265 LEA (%RSI,%R9,8),%RCX |
(658) 0x46f269 MOV %RDI,%R9 |
(658) 0x46f26c SUB %RCX,%R9 |
(658) 0x46f26f SUB $0x8,%R9 |
(658) 0x46f273 SHR $0x3,%R9 |
(658) 0x46f277 INC %R9 |
(658) 0x46f27a AND $0x7,%R9D |
(658) 0x46f27e JE 46f316 |
(658) 0x46f284 CMP $0x1,%R9 |
(658) 0x46f288 JE 46f302 |
(658) 0x46f28a CMP $0x2,%R9 |
(658) 0x46f28e JE 46f2f3 |
(658) 0x46f290 CMP $0x3,%R9 |
(658) 0x46f294 JE 46f2e4 |
(658) 0x46f296 CMP $0x4,%R9 |
(658) 0x46f29a JE 46f2d5 |
(658) 0x46f29c CMP $0x5,%R9 |
(658) 0x46f2a0 JE 46f2c6 |
(658) 0x46f2a2 CMP $0x6,%R9 |
(658) 0x46f2a6 JE 46f2b7 |
(658) 0x46f2a8 MOV (%RCX),%RAX |
(658) 0x46f2ab ADD $0x8,%RCX |
(658) 0x46f2af MOV (%R15,%RAX,8),%RSI |
(658) 0x46f2b3 MOV %RDX,(%R12,%RSI,8) |
(658) 0x46f2b7 MOV (%RCX),%R9 |
(658) 0x46f2ba ADD $0x8,%RCX |
(658) 0x46f2be MOV (%R15,%R9,8),%RAX |
(658) 0x46f2c2 MOV %RDX,(%R12,%RAX,8) |
(658) 0x46f2c6 MOV (%RCX),%RSI |
(658) 0x46f2c9 ADD $0x8,%RCX |
(658) 0x46f2cd MOV (%R15,%RSI,8),%R9 |
(658) 0x46f2d1 MOV %RDX,(%R12,%R9,8) |
(658) 0x46f2d5 MOV (%RCX),%RAX |
(658) 0x46f2d8 ADD $0x8,%RCX |
(658) 0x46f2dc MOV (%R15,%RAX,8),%RSI |
(658) 0x46f2e0 MOV %RDX,(%R12,%RSI,8) |
(658) 0x46f2e4 MOV (%RCX),%R9 |
(658) 0x46f2e7 ADD $0x8,%RCX |
(658) 0x46f2eb MOV (%R15,%R9,8),%RAX |
(658) 0x46f2ef MOV %RDX,(%R12,%RAX,8) |
(658) 0x46f2f3 MOV (%RCX),%RSI |
(658) 0x46f2f6 ADD $0x8,%RCX |
(658) 0x46f2fa MOV (%R15,%RSI,8),%R9 |
(658) 0x46f2fe MOV %RDX,(%R12,%R9,8) |
(658) 0x46f302 MOV (%RCX),%RAX |
(658) 0x46f305 ADD $0x8,%RCX |
(658) 0x46f309 MOV (%R15,%RAX,8),%RSI |
(658) 0x46f30d MOV %RDX,(%R12,%RSI,8) |
(658) 0x46f311 CMP %RCX,%RDI |
(658) 0x46f314 JE 46f38e |
(658) 0x46f316 MOV 0xe0(%RSP),%R9 |
(667) 0x46f31e MOV (%RCX),%RAX |
(667) 0x46f321 ADD $0x40,%RCX |
(667) 0x46f325 MOV (%R15,%RAX,8),%RSI |
(667) 0x46f329 MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f32d MOV -0x38(%RCX),%RAX |
(667) 0x46f331 MOV (%R15,%RAX,8),%RSI |
(667) 0x46f335 MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f339 MOV -0x30(%RCX),%RAX |
(667) 0x46f33d MOV (%R15,%RAX,8),%RSI |
(667) 0x46f341 MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f345 MOV -0x28(%RCX),%RAX |
(667) 0x46f349 MOV (%R15,%RAX,8),%RSI |
(667) 0x46f34d MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f351 MOV -0x20(%RCX),%RAX |
(667) 0x46f355 MOV (%R15,%RAX,8),%RSI |
(667) 0x46f359 MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f35d MOV -0x18(%RCX),%RAX |
(667) 0x46f361 MOV (%R15,%RAX,8),%RSI |
(667) 0x46f365 MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f369 MOV -0x10(%RCX),%RAX |
(667) 0x46f36d MOV (%R15,%RAX,8),%RSI |
(667) 0x46f371 MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f375 MOV -0x8(%RCX),%RAX |
(667) 0x46f379 MOV (%R15,%RAX,8),%RSI |
(667) 0x46f37d MOV %RDX,(%R12,%RSI,8) |
(667) 0x46f381 CMP %RCX,%RDI |
(667) 0x46f384 JNE 46f31e |
(658) 0x46f386 MOV %R9,0xe0(%RSP) |
(658) 0x46f38e MOV 0xc0(%RSP),%RCX |
(658) 0x46f396 MOV (%RCX),%RDI |
(658) 0x46f399 MOV 0x48(%RSP),%RSI |
(658) 0x46f39e MOV 0xe0(%RSP),%RCX |
(658) 0x46f3a6 VXORPD %XMM0,%XMM0,%XMM0 |
(658) 0x46f3aa VMOVSD %XMM0,%XMM0,%XMM2 |
(658) 0x46f3ae LEA (%RSI,%R8,1),%R9 |
(658) 0x46f3b2 ADD %RCX,%RSI |
(658) 0x46f3b5 MOV (%R9),%RAX |
(658) 0x46f3b8 MOV %R9,0xb0(%RSP) |
(658) 0x46f3c0 MOV %RAX,0xb8(%RSP) |
(658) 0x46f3c8 INC %RAX |
(658) 0x46f3cb CMP (%RSI),%RAX |
(658) 0x46f3ce JGE 46f4a7 |
(658) 0x46f3d4 CMPQ $0x1,0xf0(%RSP) |
(658) 0x46f3dd MOV %RBX,0xb8(%RSP) |
(658) 0x46f3e5 JE 46fae0 |
(658) 0x46f3eb MOV %R14,0x88(%RSP) |
(658) 0x46f3f3 MOV 0x20(%RSP),%R9 |
(658) 0x46f3f8 MOV %R10,0x80(%RSP) |
(658) 0x46f400 MOV 0xd0(%RSP),%R10 |
(658) 0x46f408 MOV %R13,0x78(%RSP) |
(658) 0x46f40d MOV 0x10(%RSP),%R13 |
(658) 0x46f412 NOPW (%RAX,%RAX,1) |
(666) 0x46f418 MOV (%R9,%RAX,8),%RCX |
(666) 0x46f41c CMPQ $-0x3,(%R13,%RCX,8) |
(666) 0x46f422 JE 46f43b |
(666) 0x46f424 MOV (%R10,%RCX,8),%R14 |
(666) 0x46f428 CMP %R14,(%R10,%R8,1) |
(666) 0x46f42c JNE 46f43b |
(666) 0x46f42e MOV 0xf8(%RSP),%RBX |
(666) 0x46f436 VADDSD (%RBX,%RAX,8),%XMM0,%XMM0 |
(666) 0x46f43b CMP $-0x1,%RCX |
(666) 0x46f43f JE 46f482 |
(666) 0x46f441 CMP (%R12,%RCX,8),%RDX |
(666) 0x46f445 JNE 46f482 |
(666) 0x46f447 MOV 0xf8(%RSP),%R14 |
(666) 0x46f44f LEA (,%RDI,8),%RBX |
(666) 0x46f457 VMOVSD (%R14,%RAX,8),%XMM6 |
(666) 0x46f45d MOV 0xa8(%RSP),%R14 |
(666) 0x46f465 MOV (%R14,%RCX,8),%RCX |
(666) 0x46f469 MOV 0x90(%RSP),%R14 |
(666) 0x46f471 VMOVSD %XMM6,(%R11,%RDI,8) |
(666) 0x46f477 VADDSD %XMM6,%XMM2,%XMM2 |
(666) 0x46f47b INC %RDI |
(666) 0x46f47e MOV %RCX,(%R14,%RBX,1) |
(666) 0x46f482 INC %RAX |
(666) 0x46f485 CMP (%RSI),%RAX |
(666) 0x46f488 JL 46f418 |
(658) 0x46f48a MOV 0xb8(%RSP),%RBX |
(658) 0x46f492 MOV 0x88(%RSP),%R14 |
(658) 0x46f49a MOV 0x80(%RSP),%R10 |
(658) 0x46f4a2 MOV 0x78(%RSP),%R13 |
(658) 0x46f4a7 MOV 0x60(%RSP),%R9 |
(658) 0x46f4ac MOV 0x70(%RSP),%RSI |
(658) 0x46f4b1 MOV %R9,%RAX |
(658) 0x46f4b4 MOV (%RSI,%RDX,8),%RCX |
(658) 0x46f4b8 ADD %R8,%RAX |
(658) 0x46f4bb MOV (%RAX),%RSI |
(658) 0x46f4be MOV %RAX,0xb8(%RSP) |
(658) 0x46f4c6 MOV 0x8(%R9,%R8,1),%RAX |
(658) 0x46f4cb ADD %RCX,%RAX |
(658) 0x46f4ce SUB %RSI,%RAX |
(658) 0x46f4d1 CMP %RAX,%RCX |
(658) 0x46f4d4 JGE 46f61a |
(658) 0x46f4da MOV 0x38(%RSP),%RSI |
(658) 0x46f4df MOV 0x8(%RSI),%R9 |
(658) 0x46f4e3 LEA (%R9,%RAX,8),%RSI |
(658) 0x46f4e7 LEA (%R9,%RCX,8),%RCX |
(658) 0x46f4eb MOV %RSI,%RAX |
(658) 0x46f4ee SUB %RCX,%RAX |
(658) 0x46f4f1 SUB $0x8,%RAX |
(658) 0x46f4f5 SHR $0x3,%RAX |
(658) 0x46f4f9 INC %RAX |
(658) 0x46f4fc AND $0x7,%EAX |
(658) 0x46f4ff JE 46f597 |
(658) 0x46f505 CMP $0x1,%RAX |
(658) 0x46f509 JE 46f583 |
(658) 0x46f50b CMP $0x2,%RAX |
(658) 0x46f50f JE 46f574 |
(658) 0x46f511 CMP $0x3,%RAX |
(658) 0x46f515 JE 46f565 |
(658) 0x46f517 CMP $0x4,%RAX |
(658) 0x46f51b JE 46f556 |
(658) 0x46f51d CMP $0x5,%RAX |
(658) 0x46f521 JE 46f547 |
(658) 0x46f523 CMP $0x6,%RAX |
(658) 0x46f527 JE 46f538 |
(658) 0x46f529 MOV (%RCX),%R9 |
(658) 0x46f52c ADD $0x8,%RCX |
(658) 0x46f530 MOV (%R14,%R9,8),%RAX |
(658) 0x46f534 MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f538 MOV (%RCX),%R9 |
(658) 0x46f53b ADD $0x8,%RCX |
(658) 0x46f53f MOV (%R14,%R9,8),%RAX |
(658) 0x46f543 MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f547 MOV (%RCX),%R9 |
(658) 0x46f54a ADD $0x8,%RCX |
(658) 0x46f54e MOV (%R14,%R9,8),%RAX |
(658) 0x46f552 MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f556 MOV (%RCX),%R9 |
(658) 0x46f559 ADD $0x8,%RCX |
(658) 0x46f55d MOV (%R14,%R9,8),%RAX |
(658) 0x46f561 MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f565 MOV (%RCX),%R9 |
(658) 0x46f568 ADD $0x8,%RCX |
(658) 0x46f56c MOV (%R14,%R9,8),%RAX |
(658) 0x46f570 MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f574 MOV (%RCX),%R9 |
(658) 0x46f577 ADD $0x8,%RCX |
(658) 0x46f57b MOV (%R14,%R9,8),%RAX |
(658) 0x46f57f MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f583 MOV (%RCX),%R9 |
(658) 0x46f586 ADD $0x8,%RCX |
(658) 0x46f58a MOV (%R14,%R9,8),%RAX |
(658) 0x46f58e MOV %RDX,(%RBX,%RAX,8) |
(658) 0x46f592 CMP %RCX,%RSI |
(658) 0x46f595 JE 46f60f |
(658) 0x46f597 MOV 0xe0(%RSP),%R9 |
(664) 0x46f59f MOV (%RCX),%RAX |
(664) 0x46f5a2 ADD $0x40,%RCX |
(664) 0x46f5a6 MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5aa MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5ae MOV -0x38(%RCX),%RAX |
(664) 0x46f5b2 MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5b6 MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5ba MOV -0x30(%RCX),%RAX |
(664) 0x46f5be MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5c2 MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5c6 MOV -0x28(%RCX),%RAX |
(664) 0x46f5ca MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5ce MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5d2 MOV -0x20(%RCX),%RAX |
(664) 0x46f5d6 MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5da MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5de MOV -0x18(%RCX),%RAX |
(664) 0x46f5e2 MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5e6 MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5ea MOV -0x10(%RCX),%RAX |
(664) 0x46f5ee MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5f2 MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f5f6 MOV -0x8(%RCX),%RAX |
(664) 0x46f5fa MOV (%R14,%RAX,8),%RAX |
(664) 0x46f5fe MOV %RDX,(%RBX,%RAX,8) |
(664) 0x46f602 CMP %RCX,%RSI |
(664) 0x46f605 JNE 46f59f |
(658) 0x46f607 MOV %R9,0xe0(%RSP) |
(658) 0x46f60f MOV 0xb8(%RSP),%RCX |
(658) 0x46f617 MOV (%RCX),%RSI |
(658) 0x46f61a MOV 0x50(%RSP),%RCX |
(658) 0x46f61f MOV 0xe0(%RSP),%R9 |
(658) 0x46f627 ADD %RCX,%R9 |
(658) 0x46f62a MOV (%RCX,%RDX,8),%RAX |
(658) 0x46f62e CMP %RAX,(%R9) |
(658) 0x46f631 JLE 46fc60 |
(658) 0x46f637 CMPQ $0,0x18(%RSP) |
(658) 0x46f63d JE 46fb88 |
(658) 0x46f643 MOV %R11,0x80(%RSP) |
(658) 0x46f64b MOV 0x28(%RSP),%R11 |
(658) 0x46f650 MOV %RDI,0x78(%RSP) |
(658) 0x46f655 MOV 0x8(%RSP),%RDI |
(658) 0x46f65a MOV %R12,0xe0(%RSP) |
(658) 0x46f662 MOV %R14,0x88(%RSP) |
(658) 0x46f66a JMP 46f6d9 |
0x46f66c NOPL (%RAX) |
(663) 0x46f670 MOV 0xc8(%RSP),%R14 |
(663) 0x46f678 MOV 0xd0(%RSP),%R12 |
(663) 0x46f680 MOV (%R14,%RCX,8),%R14 |
(663) 0x46f684 CMP %R14,(%R12,%R8,1) |
(663) 0x46f688 JE 46f6f8 |
(663) 0x46f68a CMP $-0x1,%RCX |
(663) 0x46f68e JE 46f6d1 |
(663) 0x46f690 CMP (%RBX,%RCX,8),%RDX |
(663) 0x46f694 JNE 46f6d1 |
(663) 0x46f696 MOV 0xe8(%RSP),%R14 |
(663) 0x46f69e LEA (,%RSI,8),%R12 |
(663) 0x46f6a6 VMOVSD (%R14,%RAX,8),%XMM7 |
(663) 0x46f6ac MOV 0xa0(%RSP),%R14 |
(663) 0x46f6b4 MOV (%R14,%RCX,8),%RCX |
(663) 0x46f6b8 MOV 0x98(%RSP),%R14 |
(663) 0x46f6c0 VMOVSD %XMM7,(%R10,%RSI,8) |
(663) 0x46f6c6 VADDSD %XMM7,%XMM2,%XMM2 |
(663) 0x46f6ca INC %RSI |
(663) 0x46f6cd MOV %RCX,(%R14,%R12,1) |
(663) 0x46f6d1 INC %RAX |
(663) 0x46f6d4 CMP (%R9),%RAX |
(663) 0x46f6d7 JGE 46f710 |
(663) 0x46f6d9 MOV (%R13,%RAX,8),%R12 |
(663) 0x46f6de MOV (%RDI,%R12,8),%RCX |
(663) 0x46f6e2 CMPQ $-0x3,(%R11,%RCX,8) |
(663) 0x46f6e7 JE 46f68a |
(663) 0x46f6e9 CMPQ $0x1,0xf0(%RSP) |
(663) 0x46f6f2 JNE 46f670 |
(663) 0x46f6f8 MOV 0xe8(%RSP),%R12 |
(663) 0x46f700 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(663) 0x46f706 JMP 46f68a |
0x46f708 NOPL (%RAX,%RAX,1) |
(658) 0x46f710 MOV 0xe0(%RSP),%R12 |
(658) 0x46f718 MOV 0x88(%RSP),%R14 |
(658) 0x46f720 MOV 0x80(%RSP),%R11 |
(658) 0x46f728 MOV 0x78(%RSP),%RDI |
(658) 0x46f72d MOV 0xb8(%RSP),%RDX |
(658) 0x46f735 MOV (%RDX),%R8 |
(658) 0x46f738 MOV 0xb0(%RSP),%RAX |
(658) 0x46f740 MOV 0xf8(%RSP),%RCX |
(658) 0x46f748 MOV (%RAX),%R9 |
(658) 0x46f74b VMULSD (%RCX,%R9,8),%XMM2,%XMM10 |
(658) 0x46f751 VCOMISD %XMM4,%XMM10 |
(658) 0x46f755 JE 46f760 |
(658) 0x46f757 VXORPD %XMM5,%XMM0,%XMM1 |
(658) 0x46f75b VDIVSD %XMM10,%XMM1,%XMM11 |
(658) 0x46f760 MOV 0xc0(%RSP),%RDX |
(658) 0x46f768 MOV (%RDX),%RCX |
(658) 0x46f76b CMP %RDI,%RCX |
(658) 0x46f76e JGE 46f8fa |
(658) 0x46f774 SUB %RCX,%RDI |
(658) 0x46f777 MOV %RCX,0xe0(%RSP) |
(658) 0x46f77f LEA -0x1(%RDI),%RAX |
(658) 0x46f783 CMP $0x2,%RAX |
(658) 0x46f787 JBE 46fcff |
(658) 0x46f78d MOV %RDI,%RDX |
(658) 0x46f790 LEA (%R11,%RCX,8),%RAX |
(658) 0x46f794 VBROADCASTSD %XMM11,%YMM12 |
(658) 0x46f799 SHR $0x2,%RDX |
(658) 0x46f79d SAL $0x5,%RDX |
(658) 0x46f7a1 LEA (%RDX,%RAX,1),%R9 |
(658) 0x46f7a5 SUB $0x20,%RDX |
(658) 0x46f7a9 SHR $0x5,%RDX |
(658) 0x46f7ad INC %RDX |
(658) 0x46f7b0 AND $0x7,%EDX |
(658) 0x46f7b3 JE 46f83d |
(658) 0x46f7b9 CMP $0x1,%RDX |
(658) 0x46f7bd JE 46f82b |
(658) 0x46f7bf CMP $0x2,%RDX |
(658) 0x46f7c3 JE 46f81e |
(658) 0x46f7c5 CMP $0x3,%RDX |
(658) 0x46f7c9 JE 46f811 |
(658) 0x46f7cb CMP $0x4,%RDX |
(658) 0x46f7cf JE 46f804 |
(658) 0x46f7d1 CMP $0x5,%RDX |
(658) 0x46f7d5 JE 46f7f7 |
(658) 0x46f7d7 CMP $0x6,%RDX |
(658) 0x46f7db JE 46f7ea |
(658) 0x46f7dd VMULPD (%RAX),%YMM12,%YMM13 |
(658) 0x46f7e1 ADD $0x20,%RAX |
(658) 0x46f7e5 VMOVUPD %YMM13,-0x20(%RAX) |
(658) 0x46f7ea VMULPD (%RAX),%YMM12,%YMM14 |
(658) 0x46f7ee ADD $0x20,%RAX |
(658) 0x46f7f2 VMOVUPD %YMM14,-0x20(%RAX) |
(658) 0x46f7f7 VMULPD (%RAX),%YMM12,%YMM15 |
(658) 0x46f7fb ADD $0x20,%RAX |
(658) 0x46f7ff VMOVUPD %YMM15,-0x20(%RAX) |
(658) 0x46f804 VMULPD (%RAX),%YMM12,%YMM0 |
(658) 0x46f808 ADD $0x20,%RAX |
(658) 0x46f80c VMOVUPD %YMM0,-0x20(%RAX) |
(658) 0x46f811 VMULPD (%RAX),%YMM12,%YMM3 |
(658) 0x46f815 ADD $0x20,%RAX |
(658) 0x46f819 VMOVUPD %YMM3,-0x20(%RAX) |
(658) 0x46f81e VMULPD (%RAX),%YMM12,%YMM2 |
(658) 0x46f822 ADD $0x20,%RAX |
(658) 0x46f826 VMOVUPD %YMM2,-0x20(%RAX) |
(658) 0x46f82b VMULPD (%RAX),%YMM12,%YMM6 |
(658) 0x46f82f ADD $0x20,%RAX |
(658) 0x46f833 VMOVUPD %YMM6,-0x20(%RAX) |
(658) 0x46f838 CMP %RAX,%R9 |
(658) 0x46f83b JE 46f8ac |
(660) 0x46f83d VMULPD (%RAX),%YMM12,%YMM7 |
(660) 0x46f841 ADD $0x100,%RAX |
(660) 0x46f847 VMULPD -0xe0(%RAX),%YMM12,%YMM8 |
(660) 0x46f84f VMULPD -0xc0(%RAX),%YMM12,%YMM9 |
(660) 0x46f857 VMULPD -0xa0(%RAX),%YMM12,%YMM10 |
(660) 0x46f85f VMULPD -0x80(%RAX),%YMM12,%YMM1 |
(660) 0x46f864 VMULPD -0x60(%RAX),%YMM12,%YMM13 |
(660) 0x46f869 VMOVUPD %YMM7,-0x100(%RAX) |
(660) 0x46f871 VMULPD -0x40(%RAX),%YMM12,%YMM14 |
(660) 0x46f876 VMOVUPD %YMM8,-0xe0(%RAX) |
(660) 0x46f87e VMULPD -0x20(%RAX),%YMM12,%YMM15 |
(660) 0x46f883 VMOVUPD %YMM9,-0xc0(%RAX) |
(660) 0x46f88b VMOVUPD %YMM10,-0xa0(%RAX) |
(660) 0x46f893 VMOVUPD %YMM1,-0x80(%RAX) |
(660) 0x46f898 VMOVUPD %YMM13,-0x60(%RAX) |
(660) 0x46f89d VMOVUPD %YMM14,-0x40(%RAX) |
(660) 0x46f8a2 VMOVUPD %YMM15,-0x20(%RAX) |
(660) 0x46f8a7 CMP %RAX,%R9 |
(660) 0x46f8aa JNE 46f83d |
(658) 0x46f8ac TEST $0x3,%DIL |
(658) 0x46f8b0 JE 46f8fa |
(658) 0x46f8b2 MOV %RDI,%R9 |
(658) 0x46f8b5 AND $-0x4,%R9 |
(658) 0x46f8b9 ADD %R9,%RCX |
(658) 0x46f8bc SUB %R9,%RDI |
(658) 0x46f8bf CMP $0x1,%RDI |
(658) 0x46f8c3 JE 46f8ee |
(658) 0x46f8c5 MOV 0xe0(%RSP),%RAX |
(658) 0x46f8cd VMOVDDUP %XMM11,%XMM12 |
(658) 0x46f8d2 ADD %R9,%RAX |
(658) 0x46f8d5 LEA (%R11,%RAX,8),%RDX |
(658) 0x46f8d9 VMULPD (%RDX),%XMM12,%XMM0 |
(658) 0x46f8dd VMOVUPD %XMM0,(%RDX) |
(658) 0x46f8e1 TEST $0x1,%DIL |
(658) 0x46f8e5 JE 46f8fa |
(658) 0x46f8e7 AND $-0x2,%RDI |
(658) 0x46f8eb ADD %RDI,%RCX |
(658) 0x46f8ee LEA (%R11,%RCX,8),%RDI |
(658) 0x46f8f2 VMULSD (%RDI),%XMM11,%XMM3 |
(658) 0x46f8f6 VMOVSD %XMM3,(%RDI) |
(658) 0x46f8fa CMP %R8,%RSI |
(658) 0x46f8fd JLE 46fa9f |
(658) 0x46f903 SUB %R8,%RSI |
(658) 0x46f906 MOV %R8,%RCX |
(658) 0x46f909 LEA -0x1(%RSI),%R9 |
(658) 0x46f90d CMP $0x2,%R9 |
(658) 0x46f911 JBE 46fd07 |
(658) 0x46f917 MOV %RSI,%RDX |
(658) 0x46f91a LEA (%R10,%R8,8),%R9 |
(658) 0x46f91e VBROADCASTSD %XMM11,%YMM6 |
(658) 0x46f923 SHR $0x2,%RDX |
(658) 0x46f927 SAL $0x5,%RDX |
(658) 0x46f92b LEA (%RDX,%R9,1),%RDI |
(658) 0x46f92f SUB $0x20,%RDX |
(658) 0x46f933 SHR $0x5,%RDX |
(658) 0x46f937 INC %RDX |
(658) 0x46f93a AND $0x7,%EDX |
(658) 0x46f93d JE 46f9d9 |
(658) 0x46f943 CMP $0x1,%RDX |
(658) 0x46f947 JE 46f9c1 |
(658) 0x46f949 CMP $0x2,%RDX |
(658) 0x46f94d JE 46f9b2 |
(658) 0x46f94f CMP $0x3,%RDX |
(658) 0x46f953 JE 46f9a3 |
(658) 0x46f955 CMP $0x4,%RDX |
(658) 0x46f959 JE 46f994 |
(658) 0x46f95b CMP $0x5,%RDX |
(658) 0x46f95f JE 46f985 |
(658) 0x46f961 CMP $0x6,%RDX |
(658) 0x46f965 JE 46f976 |
(658) 0x46f967 VMULPD (%R9),%YMM6,%YMM2 |
(658) 0x46f96c ADD $0x20,%R9 |
(658) 0x46f970 VMOVUPD %YMM2,-0x20(%R9) |
(658) 0x46f976 VMULPD (%R9),%YMM6,%YMM7 |
(658) 0x46f97b ADD $0x20,%R9 |
(658) 0x46f97f VMOVUPD %YMM7,-0x20(%R9) |
(658) 0x46f985 VMULPD (%R9),%YMM6,%YMM8 |
(658) 0x46f98a ADD $0x20,%R9 |
(658) 0x46f98e VMOVUPD %YMM8,-0x20(%R9) |
(658) 0x46f994 VMULPD (%R9),%YMM6,%YMM9 |
(658) 0x46f999 ADD $0x20,%R9 |
(658) 0x46f99d VMOVUPD %YMM9,-0x20(%R9) |
(658) 0x46f9a3 VMULPD (%R9),%YMM6,%YMM10 |
(658) 0x46f9a8 ADD $0x20,%R9 |
(658) 0x46f9ac VMOVUPD %YMM10,-0x20(%R9) |
(658) 0x46f9b2 VMULPD (%R9),%YMM6,%YMM1 |
(658) 0x46f9b7 ADD $0x20,%R9 |
(658) 0x46f9bb VMOVUPD %YMM1,-0x20(%R9) |
(658) 0x46f9c1 VMULPD (%R9),%YMM6,%YMM13 |
(658) 0x46f9c6 ADD $0x20,%R9 |
(658) 0x46f9ca VMOVUPD %YMM13,-0x20(%R9) |
(658) 0x46f9d0 CMP %R9,%RDI |
(658) 0x46f9d3 JE 46fa59 |
(659) 0x46f9d9 VMULPD (%R9),%YMM6,%YMM14 |
(659) 0x46f9de ADD $0x100,%R9 |
(659) 0x46f9e5 VMULPD -0xe0(%R9),%YMM6,%YMM15 |
(659) 0x46f9ee VMULPD -0xc0(%R9),%YMM6,%YMM12 |
(659) 0x46f9f7 VMULPD -0xa0(%R9),%YMM6,%YMM0 |
(659) 0x46fa00 VMULPD -0x80(%R9),%YMM6,%YMM3 |
(659) 0x46fa06 VMOVUPD %YMM14,-0x100(%R9) |
(659) 0x46fa0f VMULPD -0x60(%R9),%YMM6,%YMM2 |
(659) 0x46fa15 VMOVUPD %YMM15,-0xe0(%R9) |
(659) 0x46fa1e VMULPD -0x40(%R9),%YMM6,%YMM7 |
(659) 0x46fa24 VMOVUPD %YMM12,-0xc0(%R9) |
(659) 0x46fa2d VMULPD -0x20(%R9),%YMM6,%YMM8 |
(659) 0x46fa33 VMOVUPD %YMM0,-0xa0(%R9) |
(659) 0x46fa3c VMOVUPD %YMM3,-0x80(%R9) |
(659) 0x46fa42 VMOVUPD %YMM2,-0x60(%R9) |
(659) 0x46fa48 VMOVUPD %YMM7,-0x40(%R9) |
(659) 0x46fa4e VMOVUPD %YMM8,-0x20(%R9) |
(659) 0x46fa54 CMP %R9,%RDI |
(659) 0x46fa57 JNE 46f9d9 |
(658) 0x46fa59 TEST $0x3,%SIL |
(658) 0x46fa5d JE 46fa9f |
(658) 0x46fa5f MOV %RSI,%RAX |
(658) 0x46fa62 AND $-0x4,%RAX |
(658) 0x46fa66 ADD %RAX,%R8 |
(658) 0x46fa69 SUB %RAX,%RSI |
(658) 0x46fa6c CMP $0x1,%RSI |
(658) 0x46fa70 JE 46fa93 |
(658) 0x46fa72 ADD %RCX,%RAX |
(658) 0x46fa75 VMOVDDUP %XMM11,%XMM6 |
(658) 0x46fa7a LEA (%R10,%RAX,8),%RCX |
(658) 0x46fa7e VMULPD (%RCX),%XMM6,%XMM9 |
(658) 0x46fa82 VMOVUPD %XMM9,(%RCX) |
(658) 0x46fa86 TEST $0x1,%SIL |
(658) 0x46fa8a JE 46fa9f |
(658) 0x46fa8c AND $-0x2,%RSI |
(658) 0x46fa90 ADD %RSI,%R8 |
(658) 0x46fa93 LEA (%R10,%R8,8),%RSI |
(658) 0x46fa97 VMULSD (%RSI),%XMM11,%XMM10 |
(658) 0x46fa9b VMOVSD %XMM10,(%RSI) |
(658) 0x46fa9f ADDQ $0x8,0xd8(%RSP) |
(658) 0x46faa8 MOV 0xd8(%RSP),%R8 |
(658) 0x46fab0 CMP %R8,0x40(%RSP) |
(658) 0x46fab5 JNE 46f208 |
0x46fabb VZEROUPPER |
0x46fabe MOV %R12,%RDI |
0x46fac1 CALL 58f960 <hypre_Free> |
0x46fac6 LEA -0x28(%RBP),%RSP |
0x46faca MOV %RBX,%RDI |
0x46facd POP %RBX |
0x46face POP %R12 |
0x46fad0 POP %R13 |
0x46fad2 POP %R14 |
0x46fad4 POP %R15 |
0x46fad6 POP %RBP |
0x46fad7 JMP 58f960 |
0x46fadc NOPL (%RAX) |
(658) 0x46fae0 MOV %R10,0x88(%RSP) |
(658) 0x46fae8 MOV 0x10(%RSP),%R9 |
(658) 0x46faed MOV %R8,0x80(%RSP) |
(658) 0x46faf5 MOV 0x20(%RSP),%R8 |
(658) 0x46fafa NOPW (%RAX,%RAX,1) |
(665) 0x46fb00 MOV (%R8,%RAX,8),%RCX |
(665) 0x46fb04 CMPQ $-0x3,(%R9,%RCX,8) |
(665) 0x46fb09 JE 46fb18 |
(665) 0x46fb0b MOV 0xf8(%RSP),%RBX |
(665) 0x46fb13 VADDSD (%RBX,%RAX,8),%XMM0,%XMM0 |
(665) 0x46fb18 CMP $-0x1,%RCX |
(665) 0x46fb1c JE 46fb5f |
(665) 0x46fb1e CMP (%R12,%RCX,8),%RDX |
(665) 0x46fb22 JNE 46fb5f |
(665) 0x46fb24 MOV 0xf8(%RSP),%R10 |
(665) 0x46fb2c LEA (,%RDI,8),%RBX |
(665) 0x46fb34 VMOVSD (%R10,%RAX,8),%XMM3 |
(665) 0x46fb3a MOV 0xa8(%RSP),%R10 |
(665) 0x46fb42 MOV (%R10,%RCX,8),%RCX |
(665) 0x46fb46 MOV 0x90(%RSP),%R10 |
(665) 0x46fb4e VMOVSD %XMM3,(%R11,%RDI,8) |
(665) 0x46fb54 VADDSD %XMM3,%XMM2,%XMM2 |
(665) 0x46fb58 INC %RDI |
(665) 0x46fb5b MOV %RCX,(%R10,%RBX,1) |
(665) 0x46fb5f INC %RAX |
(665) 0x46fb62 CMP (%RSI),%RAX |
(665) 0x46fb65 JL 46fb00 |
(658) 0x46fb67 MOV 0xb8(%RSP),%RBX |
(658) 0x46fb6f MOV 0x88(%RSP),%R10 |
(658) 0x46fb77 MOV 0x80(%RSP),%R8 |
(658) 0x46fb7f JMP 46f4a7 |
0x46fb84 NOPL (%RAX) |
(658) 0x46fb88 CMPQ $0x1,0xf0(%RSP) |
(658) 0x46fb91 JE 46fc68 |
(658) 0x46fb97 MOV %R12,0xe0(%RSP) |
(658) 0x46fb9f MOV %R11,0x88(%RSP) |
(658) 0x46fba7 MOV %RDI,0x80(%RSP) |
(658) 0x46fbaf MOV 0x28(%RSP),%RDI |
(658) 0x46fbb4 NOPL (%RAX) |
(662) 0x46fbb8 MOV (%R13,%RAX,8),%RCX |
(662) 0x46fbbd CMPQ $-0x3,(%RDI,%RCX,8) |
(662) 0x46fbc2 JE 46fbec |
(662) 0x46fbc4 MOV 0xd0(%RSP),%R11 |
(662) 0x46fbcc MOV 0xc8(%RSP),%R12 |
(662) 0x46fbd4 MOV (%R11,%R8,1),%R11 |
(662) 0x46fbd8 CMP %R11,(%R12,%RCX,8) |
(662) 0x46fbdc JNE 46fbec |
(662) 0x46fbde MOV 0xe8(%RSP),%R12 |
(662) 0x46fbe6 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(662) 0x46fbec CMP $-0x1,%RCX |
(662) 0x46fbf0 JE 46fc34 |
(662) 0x46fbf2 CMP (%RBX,%RCX,8),%RDX |
(662) 0x46fbf6 JNE 46fc34 |
(662) 0x46fbf8 MOV 0xe8(%RSP),%R11 |
(662) 0x46fc00 LEA (,%RSI,8),%R12 |
(662) 0x46fc08 VMOVSD (%R11,%RAX,8),%XMM9 |
(662) 0x46fc0e MOV 0xa0(%RSP),%R11 |
(662) 0x46fc16 MOV (%R11,%RCX,8),%RCX |
(662) 0x46fc1a MOV 0x98(%RSP),%R11 |
(662) 0x46fc22 VMOVSD %XMM9,(%R10,%RSI,8) |
(662) 0x46fc28 VADDSD %XMM9,%XMM2,%XMM2 |
(662) 0x46fc2d INC %RSI |
(662) 0x46fc30 MOV %RCX,(%R11,%R12,1) |
(662) 0x46fc34 INC %RAX |
(662) 0x46fc37 CMP %RAX,(%R9) |
(662) 0x46fc3a JG 46fbb8 |
(658) 0x46fc40 MOV 0xe0(%RSP),%R12 |
(658) 0x46fc48 MOV 0x88(%RSP),%R11 |
(658) 0x46fc50 MOV 0x80(%RSP),%RDI |
(658) 0x46fc58 JMP 46f72d |
0x46fc5d NOPL (%RAX) |
(658) 0x46fc60 MOV %RSI,%R8 |
(658) 0x46fc63 JMP 46f738 |
(658) 0x46fc68 MOV %R11,0xe0(%RSP) |
(658) 0x46fc70 MOV %RDI,0x88(%RSP) |
(658) 0x46fc78 MOV 0x28(%RSP),%RDI |
(658) 0x46fc7d NOPL (%RAX) |
(661) 0x46fc80 MOV (%R13,%RAX,8),%RCX |
(661) 0x46fc85 CMPQ $-0x3,(%RDI,%RCX,8) |
(661) 0x46fc8a JE 46fc9a |
(661) 0x46fc8c MOV 0xe8(%RSP),%R8 |
(661) 0x46fc94 VADDSD (%R8,%RAX,8),%XMM0,%XMM0 |
(661) 0x46fc9a CMP $-0x1,%RCX |
(661) 0x46fc9e JE 46fce2 |
(661) 0x46fca0 CMP (%RBX,%RCX,8),%RDX |
(661) 0x46fca4 JNE 46fce2 |
(661) 0x46fca6 MOV 0xe8(%RSP),%R11 |
(661) 0x46fcae LEA (,%RSI,8),%R8 |
(661) 0x46fcb6 VMOVSD (%R11,%RAX,8),%XMM8 |
(661) 0x46fcbc MOV 0xa0(%RSP),%R11 |
(661) 0x46fcc4 MOV (%R11,%RCX,8),%RCX |
(661) 0x46fcc8 MOV 0x98(%RSP),%R11 |
(661) 0x46fcd0 VMOVSD %XMM8,(%R10,%RSI,8) |
(661) 0x46fcd6 VADDSD %XMM8,%XMM2,%XMM2 |
(661) 0x46fcdb INC %RSI |
(661) 0x46fcde MOV %RCX,(%R11,%R8,1) |
(661) 0x46fce2 INC %RAX |
(661) 0x46fce5 CMP %RAX,(%R9) |
(661) 0x46fce8 JG 46fc80 |
(658) 0x46fcea MOV 0xe0(%RSP),%R11 |
(658) 0x46fcf2 MOV 0x88(%RSP),%RDI |
(658) 0x46fcfa JMP 46f72d |
(658) 0x46fcff XOR %R9D,%R9D |
(658) 0x46fd02 JMP 46f8bc |
(658) 0x46fd07 XOR %EAX,%EAX |
(658) 0x46fd09 JMP 46fa69 |
0x46fd0e MOV $0x8,%ESI |
0x46fd13 MOV %RBX,%RDI |
0x46fd16 MOV %R12,0x78(%RSP) |
0x46fd1b MOV %R11,0x88(%RSP) |
0x46fd23 MOV %R10,0xb0(%RSP) |
0x46fd2b VMOVSD %XMM1,0xb8(%RSP) |
0x46fd34 MOV %RBX,0xc0(%RSP) |
0x46fd3c CALL 58f8a0 <hypre_CAlloc> |
0x46fd41 MOV 0x78(%RSP),%RCX |
0x46fd46 MOV 0xc0(%RSP),%RDX |
0x46fd4e VMOVSD 0xb8(%RSP),%XMM1 |
0x46fd57 MOV 0xb0(%RSP),%R10 |
0x46fd5f MOV %RAX,%R12 |
0x46fd62 TEST %RCX,%RCX |
0x46fd65 MOV 0x88(%RSP),%R11 |
0x46fd6d JNE 46fe26 |
0x46fd73 XOR %EBX,%EBX |
0x46fd75 TEST %RDX,%RDX |
0x46fd78 JLE 46f13f |
0x46fd7e SAL $0x3,%RDX |
0x46fd82 MOV $0xff,%ESI |
0x46fd87 MOV %R12,%RDI |
0x46fd8a MOV %RCX,0x88(%RSP) |
0x46fd92 MOV %R11,0xb0(%RSP) |
0x46fd9a MOV %R10,0xb8(%RSP) |
0x46fda2 VMOVSD %XMM1,0xc0(%RSP) |
0x46fdab CALL 4110a0 <memset@plt> |
0x46fdb0 MOV 0xb8(%RSP),%R10 |
0x46fdb8 VMOVSD 0xc0(%RSP),%XMM1 |
0x46fdc1 MOV 0xb0(%RSP),%R11 |
0x46fdc9 MOV 0x88(%RSP),%RCX |
0x46fdd1 TEST %RCX,%RCX |
0x46fdd4 JLE 46f13f |
0x46fdda LEA (,%RCX,8),%RDX |
0x46fde2 MOV $0xff,%ESI |
0x46fde7 MOV %RBX,%RDI |
0x46fdea MOV %R11,0xb0(%RSP) |
0x46fdf2 MOV %R10,0xb8(%RSP) |
0x46fdfa VMOVSD %XMM1,0xc0(%RSP) |
0x46fe03 CALL 4110a0 <memset@plt> |
0x46fe08 MOV 0xb8(%RSP),%R10 |
0x46fe10 VMOVSD 0xc0(%RSP),%XMM1 |
0x46fe19 MOV 0xb0(%RSP),%R11 |
0x46fe21 JMP 46f13f |
0x46fe26 MOV %RCX,%RDI |
0x46fe29 MOV $0x8,%ESI |
0x46fe2e MOV %R11,0x78(%RSP) |
0x46fe33 MOV %R10,0x88(%RSP) |
0x46fe3b MOV %RDX,0xb0(%RSP) |
0x46fe43 MOV %RCX,0xc0(%RSP) |
0x46fe4b VMOVSD %XMM1,0xb8(%RSP) |
0x46fe54 CALL 58f8a0 <hypre_CAlloc> |
0x46fe59 MOV 0xb0(%RSP),%RDX |
0x46fe61 MOV 0x78(%RSP),%R11 |
0x46fe66 MOV 0xc0(%RSP),%RCX |
0x46fe6e MOV 0x88(%RSP),%R10 |
0x46fe76 MOV %RAX,%RBX |
0x46fe79 VMOVSD 0xb8(%RSP),%XMM1 |
0x46fe82 TEST %RDX,%RDX |
0x46fe85 JG 46fd7e |
0x46fe8b JMP 46fdd1 |
0x46fe90 MOV %R12,%RDI |
0x46fe93 MOV $0x8,%ESI |
0x46fe98 MOV %R11,0x88(%RSP) |
0x46fea0 MOV %R10,0xb0(%RSP) |
0x46fea8 MOV %R12,0xc0(%RSP) |
0x46feb0 XOR %R12D,%R12D |
0x46feb3 VMOVSD %XMM1,0xb8(%RSP) |
0x46febc CALL 58f8a0 <hypre_CAlloc> |
0x46fec1 MOV 0xc0(%RSP),%RCX |
0x46fec9 VMOVSD 0xb8(%RSP),%XMM1 |
0x46fed2 MOV 0xb0(%RSP),%R10 |
0x46feda MOV 0x88(%RSP),%R11 |
0x46fee2 MOV %RAX,%RBX |
0x46fee5 JMP 46fdd1 |
0x46feea NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 202 |
nb uops | 215 |
loop length | 1122 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 35.83 cycles |
front end | 35.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.11-34.15 |
Stall cycles | 0.00 |
Front-end | 35.83 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 35.83 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fd0e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xd4e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fe90 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 592810 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 592800 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46fabe <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x80(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x129b57(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R8,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 58f960 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 58f960 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 58f8a0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 46fe26 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46f13f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46f13f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46f13f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 58f8a0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JG 46fd7e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdbe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 46fdd1 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 58f8a0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 46fdd1 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 202 |
nb uops | 215 |
loop length | 1122 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 35.83 cycles |
front end | 35.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.11-34.15 |
Stall cycles | 0.00 |
Front-end | 35.83 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 35.83 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fd0e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xd4e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fe90 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 592810 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 592800 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46fabe <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x80(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x129b57(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R8,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 58f960 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 58f960 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 58f8a0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 46fe26 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46f13f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46f13f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46f13f <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 58f8a0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JG 46fd7e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdbe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 46fdd1 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 58f8a0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 46fdd1 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.9– | 0.44 | 0.07 |
▼Loop 658 - par_multi_interp.c:1605-1660 - exec– | 0.08 | 0.01 |
○Loop 665 - par_multi_interp.c:1618-1628 - exec | 0.36 | 0.03 |
○Loop 664 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 660 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |
○Loop 663 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 666 - par_multi_interp.c:1618-1628 - exec | 0 | 0 |
○Loop 662 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 667 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 661 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 659 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |