Loop Id: 2997 | Module: exec | Source: ams.c:3382-3517 [...] | Coverage: 0.02% |
---|
Loop Id: 2997 | Module: exec | Source: ams.c:3382-3517 [...] | Coverage: 0.02% |
---|
0x49cf38 VMOVSD %XMM0,(%R10) |
0x49cf3d NOPL (%RAX) |
0x49cf40 MOV -0x70(%RBP),%RDX |
0x49cf44 LEA 0x1(%RDX),%RAX |
0x49cf48 CMP -0x98(%RBP),%RDX |
0x49cf4f MOV %RAX,%RDX |
0x49cf52 MOV -0x30(%RBP),%R8 |
0x49cf56 JE 49d9e0 |
0x49cf5c MOV -0x78(%RBP),%RAX |
0x49cf60 MOV %RDX,-0x70(%RBP) |
0x49cf64 LEA (%RAX,%RDX,1),%R11 |
0x49cf68 MOV -0x40(%RBP),%RAX |
0x49cf6c LEA (%RAX,%R11,8),%R10 |
0x49cf70 MOVQ $0,(%RAX,%R11,8) |
0x49cf78 TEST %R8,%R8 |
0x49cf7b JE 49d070 |
0x49cf81 MOV (%R8,%R11,8),%RDX |
0x49cf85 MOV -0x60(%RBP),%RSI |
0x49cf89 MOV (%RSI,%R11,8),%RAX |
0x49cf8d MOV 0x8(%RSI,%R11,8),%R15 |
0x49cf92 VXORPD %XMM0,%XMM0,%XMM0 |
0x49cf96 MOV %R15,%RDI |
0x49cf99 SUB %RAX,%RDI |
0x49cf9c JLE 49cff0 |
0x49cf9e CMP $0x4,%RDI |
0x49cfa2 JAE 49d12f |
0x49cfa8 MOV %RDI,%RSI |
0x49cfab AND $-0x4,%RSI |
0x49cfaf CMP %RDI,%RSI |
0x49cfb2 JAE 49cff0 |
0x49cfb4 ADD %RSI,%RAX |
0x49cfb7 MOV -0x30(%RBP),%RDI |
0x49cfbb JMP 49cfc8 |
(3006) 0x49cfc0 INC %RAX |
(3006) 0x49cfc3 CMP %RAX,%R15 |
(3006) 0x49cfc6 JE 49cff0 |
(3006) 0x49cfc8 MOV (%R13,%RAX,8),%RSI |
(3006) 0x49cfcd CMP (%RDI,%RSI,8),%RDX |
(3006) 0x49cfd1 JNE 49cfc0 |
(3006) 0x49cfd3 VMOVSD (%R14,%RAX,8),%XMM1 |
(3006) 0x49cfd9 VANDPD %XMM5,%XMM1,%XMM1 |
(3006) 0x49cfdd VADDSD %XMM1,%XMM0,%XMM0 |
(3006) 0x49cfe1 VMOVSD %XMM0,(%R10) |
(3006) 0x49cfe6 JMP 49cfc0 |
0x49cff0 CMPQ $0,-0x88(%RBP) |
0x49cff8 MOV -0x48(%RBP),%R15 |
0x49cffc JE 49cf40 |
0x49d002 MOV -0x80(%RBP),%RSI |
0x49d006 MOV (%RSI,%R11,8),%RAX |
0x49d00a MOV 0x8(%RSI,%R11,8),%R11 |
0x49d00f MOV %R11,%R8 |
0x49d012 SUB %RAX,%R8 |
0x49d015 JLE 49cf40 |
0x49d01b CMP $0x4,%R8 |
0x49d01f JAE 49d1e5 |
0x49d025 MOV %R8,%RSI |
0x49d028 AND $-0x4,%RSI |
0x49d02c CMP %R8,%RSI |
0x49d02f JAE 49cf40 |
0x49d035 ADD %RSI,%RAX |
0x49d038 JMP 49d04c |
(3004) 0x49d040 INC %RAX |
(3004) 0x49d043 CMP %RAX,%R11 |
(3004) 0x49d046 JE 49cf40 |
(3004) 0x49d04c MOV (%R12,%RAX,8),%RSI |
(3004) 0x49d050 CMP (%R15,%RSI,8),%RDX |
(3004) 0x49d054 JNE 49d040 |
(3004) 0x49d056 VMOVSD (%RBX,%RAX,8),%XMM1 |
(3004) 0x49d05b VANDPD %XMM5,%XMM1,%XMM1 |
(3004) 0x49d05f VADDSD %XMM1,%XMM0,%XMM0 |
(3004) 0x49d063 VMOVSD %XMM0,(%R10) |
(3004) 0x49d068 JMP 49d040 |
0x49d070 MOV -0x60(%RBP),%RAX |
0x49d074 MOV (%RAX,%R11,8),%RDX |
0x49d078 MOV 0x8(%RAX,%R11,8),%RAX |
0x49d07d VXORPD %XMM0,%XMM0,%XMM0 |
0x49d081 MOV %RAX,%RDI |
0x49d084 SUB %RDX,%RDI |
0x49d087 JLE 49d0cb |
0x49d089 LEA -0x8(%R14,%RAX,8),%RSI |
0x49d08e LEA (%R14,%RDX,8),%R8 |
0x49d092 CMP %R10,%RSI |
0x49d095 JB 49d288 |
0x49d09b CMP %R8,%R10 |
0x49d09e JB 49d288 |
0x49d0a4 NOPW %CS:(%RAX,%RAX,1) |
(3003) 0x49d0b0 VMOVSD (%R14,%RDX,8),%XMM1 |
(3003) 0x49d0b6 VANDPD %XMM5,%XMM1,%XMM1 |
(3003) 0x49d0ba VADDSD %XMM1,%XMM0,%XMM0 |
(3003) 0x49d0be VMOVSD %XMM0,(%R10) |
(3003) 0x49d0c3 INC %RDX |
(3003) 0x49d0c6 CMP %RDX,%RAX |
(3003) 0x49d0c9 JNE 49d0b0 |
0x49d0cb CMPQ $0,-0x88(%RBP) |
0x49d0d3 JE 49cf40 |
0x49d0d9 MOV -0x80(%RBP),%RAX |
0x49d0dd MOV (%RAX,%R11,8),%RDX |
0x49d0e1 MOV 0x8(%RAX,%R11,8),%RAX |
0x49d0e6 MOV %RAX,%RDI |
0x49d0e9 SUB %RDX,%RDI |
0x49d0ec JLE 49cf40 |
0x49d0f2 LEA -0x8(%RBX,%RAX,8),%RSI |
0x49d0f7 LEA (%RBX,%RDX,8),%R8 |
0x49d0fb CMP %R10,%RSI |
0x49d0fe JB 49d2d1 |
0x49d104 CMP %R8,%R10 |
0x49d107 JB 49d2d1 |
0x49d10d NOPL (%RAX) |
(3000) 0x49d110 VMOVSD (%RBX,%RDX,8),%XMM1 |
(3000) 0x49d115 VANDPD %XMM5,%XMM1,%XMM1 |
(3000) 0x49d119 VADDSD %XMM1,%XMM0,%XMM0 |
(3000) 0x49d11d VMOVSD %XMM0,(%R10) |
(3000) 0x49d122 INC %RDX |
(3000) 0x49d125 CMP %RDX,%RAX |
(3000) 0x49d128 JNE 49d110 |
0x49d12a JMP 49cf40 |
0x49d12f MOV %RDI,%R8 |
0x49d132 SHR $0x2,%R8 |
0x49d136 LEA 0x18(,%RAX,8),%RSI |
0x49d13e JMP 49d151 |
(3007) 0x49d140 MOV -0x50(%RBP),%R12 |
(3007) 0x49d144 ADD $0x20,%RSI |
(3007) 0x49d148 DEC %R8 |
(3007) 0x49d14b JE 49cfa8 |
(3007) 0x49d151 MOV -0x18(%R13,%RSI,1),%R9 |
(3007) 0x49d156 MOV -0x30(%RBP),%R12 |
(3007) 0x49d15a CMP (%R12,%R9,8),%RDX |
(3007) 0x49d15e JNE 49d174 |
(3007) 0x49d160 VMOVSD -0x18(%R14,%RSI,1),%XMM1 |
(3007) 0x49d167 VANDPD %XMM5,%XMM1,%XMM1 |
(3007) 0x49d16b VADDSD %XMM1,%XMM0,%XMM0 |
(3007) 0x49d16f VMOVSD %XMM0,(%R10) |
(3007) 0x49d174 MOV -0x10(%R13,%RSI,1),%R9 |
(3007) 0x49d179 MOV -0x30(%RBP),%R12 |
(3007) 0x49d17d CMP (%R12,%R9,8),%RDX |
(3007) 0x49d181 JNE 49d197 |
(3007) 0x49d183 VMOVSD -0x10(%R14,%RSI,1),%XMM1 |
(3007) 0x49d18a VANDPD %XMM5,%XMM1,%XMM1 |
(3007) 0x49d18e VADDSD %XMM1,%XMM0,%XMM0 |
(3007) 0x49d192 VMOVSD %XMM0,(%R10) |
(3007) 0x49d197 MOV -0x8(%R13,%RSI,1),%R9 |
(3007) 0x49d19c MOV -0x30(%RBP),%R12 |
(3007) 0x49d1a0 CMP (%R12,%R9,8),%RDX |
(3007) 0x49d1a4 JNE 49d1ba |
(3007) 0x49d1a6 VMOVSD -0x8(%R14,%RSI,1),%XMM1 |
(3007) 0x49d1ad VANDPD %XMM5,%XMM1,%XMM1 |
(3007) 0x49d1b1 VADDSD %XMM1,%XMM0,%XMM0 |
(3007) 0x49d1b5 VMOVSD %XMM0,(%R10) |
(3007) 0x49d1ba MOV (%R13,%RSI,1),%R9 |
(3007) 0x49d1bf MOV -0x30(%RBP),%R12 |
(3007) 0x49d1c3 CMP (%R12,%R9,8),%RDX |
(3007) 0x49d1c7 JNE 49d140 |
(3007) 0x49d1cd VMOVSD (%R14,%RSI,1),%XMM1 |
(3007) 0x49d1d3 VANDPD %XMM5,%XMM1,%XMM1 |
(3007) 0x49d1d7 VADDSD %XMM1,%XMM0,%XMM0 |
(3007) 0x49d1db VMOVSD %XMM0,(%R10) |
(3007) 0x49d1e0 JMP 49d140 |
0x49d1e5 MOV %R8,%RDI |
0x49d1e8 SHR $0x2,%RDI |
0x49d1ec LEA 0x18(,%RAX,8),%RSI |
0x49d1f4 JMP 49d20d |
(3005) 0x49d200 ADD $0x20,%RSI |
(3005) 0x49d204 DEC %RDI |
(3005) 0x49d207 JE 49d025 |
(3005) 0x49d20d MOV -0x18(%R12,%RSI,1),%R9 |
(3005) 0x49d212 CMP (%R15,%R9,8),%RDX |
(3005) 0x49d216 JNE 49d22b |
(3005) 0x49d218 VMOVSD -0x18(%RBX,%RSI,1),%XMM1 |
(3005) 0x49d21e VANDPD %XMM5,%XMM1,%XMM1 |
(3005) 0x49d222 VADDSD %XMM1,%XMM0,%XMM0 |
(3005) 0x49d226 VMOVSD %XMM0,(%R10) |
(3005) 0x49d22b MOV -0x10(%R12,%RSI,1),%R9 |
(3005) 0x49d230 CMP (%R15,%R9,8),%RDX |
(3005) 0x49d234 JNE 49d249 |
(3005) 0x49d236 VMOVSD -0x10(%RBX,%RSI,1),%XMM1 |
(3005) 0x49d23c VANDPD %XMM5,%XMM1,%XMM1 |
(3005) 0x49d240 VADDSD %XMM1,%XMM0,%XMM0 |
(3005) 0x49d244 VMOVSD %XMM0,(%R10) |
(3005) 0x49d249 MOV -0x8(%R12,%RSI,1),%R9 |
(3005) 0x49d24e CMP (%R15,%R9,8),%RDX |
(3005) 0x49d252 JNE 49d267 |
(3005) 0x49d254 VMOVSD -0x8(%RBX,%RSI,1),%XMM1 |
(3005) 0x49d25a VANDPD %XMM5,%XMM1,%XMM1 |
(3005) 0x49d25e VADDSD %XMM1,%XMM0,%XMM0 |
(3005) 0x49d262 VMOVSD %XMM0,(%R10) |
(3005) 0x49d267 MOV (%R12,%RSI,1),%R9 |
(3005) 0x49d26b CMP (%R15,%R9,8),%RDX |
(3005) 0x49d26f JNE 49d200 |
(3005) 0x49d271 VMOVSD (%RBX,%RSI,1),%XMM1 |
(3005) 0x49d276 VANDPD %XMM5,%XMM1,%XMM1 |
(3005) 0x49d27a VADDSD %XMM1,%XMM0,%XMM0 |
(3005) 0x49d27e VMOVSD %XMM0,(%R10) |
(3005) 0x49d283 JMP 49d200 |
0x49d288 MOV %RDI,%RSI |
0x49d28b AND $-0x4,%RSI |
0x49d28f JE 49d329 |
0x49d295 LEA -0x1(%RSI),%R15 |
0x49d299 VXORPD %XMM0,%XMM0,%XMM0 |
0x49d29d XOR %R9D,%R9D |
(3002) 0x49d2a0 VANDPD (%R8,%R9,8),%YMM6,%YMM1 |
(3002) 0x49d2a6 VADDPD %YMM1,%YMM0,%YMM0 |
(3002) 0x49d2aa ADD $0x4,%R9 |
(3002) 0x49d2ae CMP %R15,%R9 |
(3002) 0x49d2b1 JBE 49d2a0 |
0x49d2b3 VEXTRACTF128 $0x1,%YMM0,%XMM1 |
0x49d2b9 VADDPD %XMM1,%XMM0,%XMM0 |
0x49d2bd VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
0x49d2c2 VADDSD %XMM1,%XMM0,%XMM0 |
0x49d2c6 CMP %RSI,%RDI |
0x49d2c9 MOV -0x48(%RBP),%R15 |
0x49d2cd JNE 49d32b |
0x49d2cf JMP 49d346 |
0x49d2d1 MOV %RDI,%RSI |
0x49d2d4 AND $-0x4,%RSI |
0x49d2d8 JE 49d35e |
0x49d2de LEA -0x1(%RSI),%R11 |
0x49d2e2 VXORPD %XMM1,%XMM1,%XMM1 |
0x49d2e6 XOR %R15D,%R15D |
0x49d2e9 NOPL (%RAX) |
(2999) 0x49d2f0 VANDPD (%R8,%R15,8),%YMM6,%YMM2 |
(2999) 0x49d2f6 VADDPD %YMM2,%YMM1,%YMM1 |
(2999) 0x49d2fa ADD $0x4,%R15 |
(2999) 0x49d2fe CMP %R11,%R15 |
(2999) 0x49d301 JBE 49d2f0 |
0x49d303 VEXTRACTF128 $0x1,%YMM1,%XMM2 |
0x49d309 VADDPD %XMM2,%XMM1,%XMM1 |
0x49d30d VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 |
0x49d312 VADDSD %XMM2,%XMM1,%XMM1 |
0x49d316 VADDSD %XMM1,%XMM0,%XMM0 |
0x49d31a CMP %RSI,%RDI |
0x49d31d MOV -0x48(%RBP),%R15 |
0x49d321 JE 49cf38 |
0x49d327 JMP 49d360 |
0x49d329 XOR %ESI,%ESI |
0x49d32b ADD %RDX,%RSI |
0x49d32e XCHG %AX,%AX |
(3001) 0x49d330 VMOVSD (%R14,%RSI,8),%XMM1 |
(3001) 0x49d336 VANDPD %XMM5,%XMM1,%XMM1 |
(3001) 0x49d33a VADDSD %XMM1,%XMM0,%XMM0 |
(3001) 0x49d33e INC %RSI |
(3001) 0x49d341 CMP %RSI,%RAX |
(3001) 0x49d344 JNE 49d330 |
0x49d346 VMOVSD %XMM0,(%R10) |
0x49d34b CMPQ $0,-0x88(%RBP) |
0x49d353 JNE 49d0d9 |
0x49d359 JMP 49cf40 |
0x49d35e XOR %ESI,%ESI |
0x49d360 ADD %RDX,%RSI |
0x49d363 NOPW %CS:(%RAX,%RAX,1) |
(2998) 0x49d370 VMOVSD (%RBX,%RSI,8),%XMM1 |
(2998) 0x49d375 VANDPD %XMM5,%XMM1,%XMM1 |
(2998) 0x49d379 VADDSD %XMM1,%XMM0,%XMM0 |
(2998) 0x49d37d INC %RSI |
(2998) 0x49d380 CMP %RSI,%RAX |
(2998) 0x49d383 JNE 49d370 |
0x49d385 JMP 49cf38 |
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3517 |
-------------------------------------------------------------------------------- |
3382: for (i = ns; i < ne; i++) |
3383: { |
3384: l1_norm[i] = 0.0; |
3385: if (cf_marker == NULL) |
3386: { |
3387: /* Add the l1 norm of the diag part of the ith row */ |
3388: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3389: l1_norm[i] += fabs(A_diag_data[j]); |
3390: /* Add the l1 norm of the offd part of the ith row */ |
3391: if (num_cols_offd) |
3392: { |
3393: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
3394: l1_norm[i] += fabs(A_offd_data[j]); |
3395: } |
3396: } |
3397: else |
3398: { |
3399: cf_diag = cf_marker[i]; |
3400: /* Add the CF l1 norm of the diag part of the ith row */ |
3401: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3402: if (cf_diag == cf_marker[A_diag_J[j]]) |
3403: l1_norm[i] += fabs(A_diag_data[j]); |
3404: /* Add the CF l1 norm of the offd part of the ith row */ |
3405: if (num_cols_offd) |
3406: { |
3407: for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++) |
3408: if (cf_diag == cf_marker_offd[A_offd_J[j]]) |
3409: l1_norm[i] += fabs(A_offd_data[j]); |
[...] |
3473: if (cf_marker == NULL) |
[...] |
3517: if (num_cols_offd) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.05 |
CQA speedup if FP arith vectorized | 2.91 |
CQA speedup if fully vectorized | 11.66 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3382-3385,ams.c:3388-3394,ams.c:3399-3401,ams.c:3405-3409,ams.c:3473-3473,ams.c:3517-3517 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.50 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 7.40 |
CQA cycles if fully vectorized | 1.84 |
Front-end cycles | 21.50 |
DIV/SQRT cycles | 12.10 |
P0 cycles | 12.30 |
P1 cycles | 8.33 |
P2 cycles | 8.33 |
P3 cycles | 2.00 |
P4 cycles | 12.30 |
P5 cycles | 12.10 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 12.20 |
P10 cycles | 8.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 21.76 |
Stall cycles (UFS) | 0.00 |
Nb insns | 129.00 |
Nb uops | 129.00 |
Nb loads | 25.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.33 |
Nb FLOP add-sub | 7.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.79 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 21.28 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.67 |
Vector-efficiency ratio all | 14.76 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 10.94 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.42 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.05 |
CQA speedup if FP arith vectorized | 2.91 |
CQA speedup if fully vectorized | 11.66 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3382-3385,ams.c:3388-3394,ams.c:3399-3401,ams.c:3405-3409,ams.c:3473-3473,ams.c:3517-3517 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.50 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 7.40 |
CQA cycles if fully vectorized | 1.84 |
Front-end cycles | 21.50 |
DIV/SQRT cycles | 12.10 |
P0 cycles | 12.30 |
P1 cycles | 8.33 |
P2 cycles | 8.33 |
P3 cycles | 2.00 |
P4 cycles | 12.30 |
P5 cycles | 12.10 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 12.20 |
P10 cycles | 8.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 21.76 |
Stall cycles (UFS) | 0.00 |
Nb insns | 129.00 |
Nb uops | 129.00 |
Nb loads | 25.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.33 |
Nb FLOP add-sub | 7.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.79 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 21.28 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 26.67 |
Vector-efficiency ratio all | 14.76 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 10.94 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.42 |
Path / |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3382-3517 |
Module | exec |
nb instructions | 129 |
nb uops | 129 |
loop length | 556 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 21.50 cycles |
front end | 21.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
cycles | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 21.76 |
Stall cycles | 0.00 |
Front-end | 21.50 |
Dispatch | 12.30 |
Overall L1 | 21.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 40% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 21% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 11% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 20% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 17% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 49d9e0 <hypre_ParCSRComputeL1NormsThreads.extracted+0x16e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVQ $0,(%RAX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 49d070 <hypre_ParCSRComputeL1NormsThreads.extracted+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R8,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49cff0 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcf0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49d12f <hypre_ParCSRComputeL1NormsThreads.extracted+0xe2f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49cff0 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcf0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 49cfc8 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcc8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
CMPQ $0,-0x88(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49d1e5 <hypre_ParCSRComputeL1NormsThreads.extracted+0xee5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 49d04c <hypre_ParCSRComputeL1NormsThreads.extracted+0xd4c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49d0cb <hypre_ParCSRComputeL1NormsThreads.extracted+0xdcb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%R14,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R14,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d288 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf88> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d288 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf88> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0x88(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%RBX,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RBX,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d2d1 <hypre_ParCSRComputeL1NormsThreads.extracted+0xfd1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d2d1 <hypre_ParCSRComputeL1NormsThreads.extracted+0xfd1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RDI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49d151 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe51> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49d20d <hypre_ParCSRComputeL1NormsThreads.extracted+0xf0d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 49d329 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1029> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x48(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 49d32b <hypre_ParCSRComputeL1NormsThreads.extracted+0x102b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 49d346 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1046> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 49d35e <hypre_ParCSRComputeL1NormsThreads.extracted+0x105e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x48(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 49cf38 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc38> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 49d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1060> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0x88(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 49d0d9 <hypre_ParCSRComputeL1NormsThreads.extracted+0xdd9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49cf38 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc38> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3382-3517 |
Module | exec |
nb instructions | 129 |
nb uops | 129 |
loop length | 556 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 21.50 cycles |
front end | 21.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
cycles | 12.10 | 12.30 | 8.33 | 8.33 | 2.00 | 12.30 | 12.10 | 2.00 | 2.00 | 2.00 | 12.20 | 8.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 21.76 |
Stall cycles | 0.00 |
Front-end | 21.50 |
Dispatch | 12.30 |
Overall L1 | 21.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 40% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 21% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 26% |
all | 11% |
load | 12% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 20% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 17% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 15% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0x98(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 49d9e0 <hypre_ParCSRComputeL1NormsThreads.extracted+0x16e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%R11,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVQ $0,(%RAX,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 49d070 <hypre_ParCSRComputeL1NormsThreads.extracted+0xd70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R8,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49cff0 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcf0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49d12f <hypre_ParCSRComputeL1NormsThreads.extracted+0xe2f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49cff0 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcf0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 49cfc8 <hypre_ParCSRComputeL1NormsThreads.extracted+0xcc8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
CMPQ $0,-0x88(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RSI,%R11,8),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49d1e5 <hypre_ParCSRComputeL1NormsThreads.extracted+0xee5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JMP 49d04c <hypre_ParCSRComputeL1NormsThreads.extracted+0xd4c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49d0cb <hypre_ParCSRComputeL1NormsThreads.extracted+0xdcb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%R14,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R14,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d288 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf88> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d288 <hypre_ParCSRComputeL1NormsThreads.extracted+0xf88> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0x88(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x80(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%R11,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RAX,%R11,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x8(%RBX,%RAX,8),%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RBX,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d2d1 <hypre_ParCSRComputeL1NormsThreads.extracted+0xfd1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 49d2d1 <hypre_ParCSRComputeL1NormsThreads.extracted+0xfd1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RDI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49d151 <hypre_ParCSRComputeL1NormsThreads.extracted+0xe51> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49d20d <hypre_ParCSRComputeL1NormsThreads.extracted+0xf0d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 49d329 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1029> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x48(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 49d32b <hypre_ParCSRComputeL1NormsThreads.extracted+0x102b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 49d346 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1046> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 49d35e <hypre_ParCSRComputeL1NormsThreads.extracted+0x105e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%RSI),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x48(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 49cf38 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc38> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 49d360 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1060> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMPQ $0,-0x88(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 49d0d9 <hypre_ParCSRComputeL1NormsThreads.extracted+0xdd9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 49cf40 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 49cf38 <hypre_ParCSRComputeL1NormsThreads.extracted+0xc38> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |